On 15 January 2015 at 13:38, Lars Doelle <[email protected]> wrote: > Hi everyone, > > > working on the dts for an A20 device, I'm currently at the nand. > > Looking at Documentation/devicetree/bindings/mtd/sunxi-nand.txt, > there are two parts in the example, that do not really make sense > to me: > > 1) interrupts > > Does anyone know what interrupt is refered to in the example? > The A20 handbook lists GIC 69 for NAND, while 37 in the example > is IR 0.
iirc the GIC interrupt numbers are offset by some value like 32 compared to the pre-GIC (sun4i and sun5i) SoC interrupt numbers. This is easy to see in the sunxi 3.4 kernel sources but not so clear on mainline I guess. arch/arm/plat-sunxi/include/plat/irqs.h:#define AW_IRQ_GIC_START 32 > 2) pinctrl-0 > > If I understand correctly, I'd setup two pinctrl groups, > one for all pins with function "nand0", i.e. PC00 to PC18. > PC19-PC22 are not mentioned in my FEX, so I'd leave the > later out. > > PC23 has function "spi0" and goes to the second group. > > I'd leave out any allwinner,pull and allwinner,drive > properties for these groups assuming pinctrl derives > them from the functions. > > Now what puzzles me is, that in the example three groups > are setup distinguishing nand_pins_a and nand_rb0_pins_a, > though they have all the same function "nand0". Do I > misunderstand anything at that point, or is this grouping > just a matter of personal style? This is probably a matter of some hardware layout rather than style. eg. the A/B/C/... pin groups loosely correspond to some sections of the SoC BGA package. Also the pin names and pin groups probably correspond to some Allwinner document so if they named some pins nand and other pins nand_rb0 then that is what they are named. Thanks Michal -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
