On Thu, Jan 15, 2015 at 01:38:03PM +0100, Lars Doelle wrote:
> Hi everyone,
> 
> 
> working on the dts for an A20 device, I'm currently at the nand.

I assume you are aware of the current state of the NAND, right?

> Looking at Documentation/devicetree/bindings/mtd/sunxi-nand.txt,
> there are two parts in the example, that do not really make sense
> to me:
> 
> 1) interrupts
> 
>    Does anyone know what interrupt is refered to in the example?
>    The A20 handbook lists GIC 69 for NAND, while 37 in the example
>    is IR 0.

All the GIC interrupts above 32 are SPIs. 69 - 32 = 37

> 2) pinctrl-0
> 
>    If I understand correctly, I'd setup two pinctrl groups,
>    one for all pins with function "nand0", i.e. PC00 to PC18.
>    PC19-PC22 are not mentioned in my FEX, so I'd leave the
>    later out.
> 
>    PC23 has function "spi0" and goes to the second group.

I don't really know what you want to achieve, but it sounds sensible,
even though I don't really know why SPI0 is involved here.

>    I'd leave out any allwinner,pull and allwinner,drive
>    properties for these groups assuming pinctrl derives
>    them from the functions.

No. I cannot derive anything from any function.

>    Now what puzzles me is, that in the example three groups
>    are setup distinguishing nand_pins_a and nand_rb0_pins_a,
>    though they have all the same function "nand0". Do I
>    misunderstand anything at that point, or is this grouping
>    just a matter of personal style?

R/B and CS pins are optional and this configuration change to one from
another.

If your board use both the nand controller pins to do that, you need
to mux them, but your board might not use them, or use GPIOs instead
for example. In order to support the most cases, we split it into
three groups: the main pins (needed by anyone), the rb pins and the cs
pins.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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