[ I realized I replied to v2 and not v4 as the thread of v2 pushed that to the top. I'll repeat my statement here too. ]
On Thu, 15 Oct 2026 19:32:34 +0200 Roman 'Hedin' Storozhenko <[email protected]> wrote: > diff --git a/include/trace/events/riscv_tlb.h > b/include/trace/events/riscv_tlb.h Please do not put architecture specific events in include/trace. They belong in the architecture. See the example code in samples/trace_events/trace-events-sample.[ch] as well as the Makefile there on how to put trace events in directories outside of include/trace/ Thanks, -- Steve > new file mode 100644 > index 000000000000..f289480a2c0e > --- /dev/null > +++ b/include/trace/events/riscv_tlb.h > @@ -0,0 +1,90 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#undef TRACE_SYSTEM > +#define TRACE_SYSTEM riscv_tlb > + > +#if !defined(_TRACE_RISCV_TLB_H) || defined(TRACE_HEADER_MULTI_READ) > +#define _TRACE_RISCV_TLB_H > + > +#include <linux/cpumask.h> > +#include <linux/tracepoint.h> > + > +#ifndef _TRACE_RISCV_TLB_ENUMS > +#define _TRACE_RISCV_TLB_ENUMS > + > +enum riscv_tlb_flush_scope { > + RISCV_TLB_FLUSH_SCOPE_SINGLE, > + RISCV_TLB_FLUSH_SCOPE_RANGE, > + RISCV_TLB_FLUSH_SCOPE_ADDRESS_SPACE, > + RISCV_TLB_FLUSH_SCOPE_ALL, > +}; > + > +#endif /* _TRACE_RISCV_TLB_ENUMS */ > + > +TRACE_DEFINE_ENUM(RISCV_TLB_FLUSH_SCOPE_SINGLE); > +TRACE_DEFINE_ENUM(RISCV_TLB_FLUSH_SCOPE_RANGE); > +TRACE_DEFINE_ENUM(RISCV_TLB_FLUSH_SCOPE_ADDRESS_SPACE); > +TRACE_DEFINE_ENUM(RISCV_TLB_FLUSH_SCOPE_ALL); > + > +#define show_riscv_tlb_flush_scope(scope) \ > + __print_symbolic(scope, \ > + { RISCV_TLB_FLUSH_SCOPE_SINGLE, "single" }, \ > + { RISCV_TLB_FLUSH_SCOPE_RANGE, "range" }, \ > + { RISCV_TLB_FLUSH_SCOPE_ADDRESS_SPACE, "address-space" }, \ > + { RISCV_TLB_FLUSH_SCOPE_ALL, "all" }) > + > +/* > + * Record the invalidation request received by the RISC-V architecture code > + * > + * The target CPU mask represents the CPUs Linux intends to cover for the > + * request. It can be correlated with per-CPU activity, but does not describe > + * which harts ultimately performed an invalidation. > + * > + * The ASID is hardware-visible and may be reused. It must not be treated as > a > + * persistent identifier for an mm. > + * > + * The stride describes the invalidation granularity supplied to the RISC-V > + * implementation. > + * > + * The event records the invalidation request before it is dispatched. It > does > + * not describe the mechanism used to execute the request. > + * > + */ > +TRACE_EVENT(riscv_tlb_flush_request, > + TP_PROTO(unsigned long start, unsigned long size, > + unsigned long stride, unsigned long asid, bool has_mm, > + const struct cpumask *cmask, > + enum riscv_tlb_flush_scope scope), > + > + TP_ARGS(start, size, stride, asid, has_mm, cmask, scope), > + > + TP_STRUCT__entry(__field(unsigned long, start) > + __field(unsigned long, size) > + __field(unsigned long, stride) > + __field(unsigned long, asid) > + __field(bool, has_mm) > + __field(unsigned int, target_mask_weight) > + __cpumask(target_cpus) > + __field(u8, scope) > + ), > + > + TP_fast_assign(__entry->start = start; > + __entry->size = size; > + __entry->stride = stride; > + __entry->asid = asid; > + __entry->has_mm = has_mm; > + __entry->target_mask_weight = cpumask_weight(cmask); > + __assign_cpumask(target_cpus, cpumask_bits(cmask)); > + __entry->scope = scope; > + ), > + > + TP_printk("start=%#lx size=%#lx stride=%#lx asid=%#lx has_mm=%d > target_mask_weight=%u target_cpus=%s scope=%s", > + __entry->start, __entry->size, __entry->stride, > + __entry->asid, __entry->has_mm, > + __entry->target_mask_weight, __get_cpumask(target_cpus), > + show_riscv_tlb_flush_scope(__entry->scope)) > +); > + > +#endif /* _TRACE_RISCV_TLB_H */ > + > +/* This part must be outside protection. */ > +#include <trace/define_trace.h>
