No, IPR is set _implicitly_ when the FIFO fills ... that's
why it's only set _explicitly_ to send short packets.
Interesting.. The UDC docs say for me that I need to set it to send the first packet... And once I removed the printk's, I no longer had the resetting issue.
If you're thinking about the text I know about (algorithmic description, disagreeing with how UDCCS0_IPR is specified), that was updated in the Feb-2003 pxa250/210 spec update (D68) to basically match the pxa255 text (and the UDCCS0_IPR spec, which always said "must not" set IPR for full packets).
The hardware's very sensitive about handling of IPR and OPR... were you able to run the control traffic regression tests without any failures? For how long? That does a reasonably good job of running through the most significant code paths, and making them all work wasn't straightforward.
I'm telling you, whoever designed the UDC must've had obsessive-compulsive disorder... "Is the packet there yet? Yet? How about now? *pokepokepokepoke*" "YES IT'S THERE!" ".. oh, ok. Can I send it yet? Yet? How about now?" ....
That wouldn't explain UDCCS0_IPR ... since IPR "always reads as zero", there's no explicit way to answer the "Can I send it yet?" question!!
Or the way the control STATUS stage can start at any instant after the DATA stage starts, causing device states which can't be inferred using just the model (and procedures) from Intel's documentation.
Anyway, handhelds.org CVS seems to "work". Well, except for that, uh, issue where, uh, OUT packets in bulk just stopped working. But I'll debug that Soon. :)
Do you see that only on pxa250 B1 silicon? How about C0?
pxa255 is solid for me: Weeks of continuous tests, no errors, and no intermittent problems.
Correction. They work every other boot. (Actually, not every other boot - maybe one in eight boots. What the @#$%?)
Let's hope it's not clockspeed! (I use 200 MHz.) But I suspect it was just luck (and long delays from debug messages) that made it work with those changes.
- Dave
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