Hi all.
Thank for some information of ARM procceser.
>The minimum pulse width requirements for PXA250, 255 and 270 are
>according to the corresponding Developer's Manuals:
> 1000ns for PXA250
> 290ns for PXA255
> 154ns for PXA270 (from "PXA270 Electrical, Mechanical and Thermal Spec.")
Some board like INTEL sitsang,Interrupt signal is not connected directly to cpu.
Interrupt signal is connected to PLD (perhaps flipflop type D-Latch in it,it is hold
rising edge.)
And I think cpu can clear this flipflop type D-Latch after interrupt.
So pulse width is not problem here.
I wonder if LEVEL trigger is not handle by PXA2xx?
BY THE WAY
I test as below[send mail yesterday]
printk("i%d\n",iso_buffer_index);HERE added 'i' 040909
But sometime I met bable or kernel panic
a
i0
11
i1
8
i0
i0
a
10
ov511.c: ERROR: urb->status=-75: Babble (bad cable?)
i1
i0
i0
b
10
ov511.c: ERROR: urb->status=-75: Babble (bad cable?)
Right sequence is shown as below.
a
i0
11
i1
a
i0
11
i1
Adsynori
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