Hi,

Ian Campbell writes:
> It's IRQ 25 (GPIO 2) and the HcHardwareConfig used in the 2.4 driver is
> InterruptOutputPolarity|InterruptPinTrigger|DataBusWidth16|DREQOutputPolarity|DownstreamPort15KRSel|AnalogOCEnable
> 
> I make that active high, edge triggered. The GPIO line is setup as
> GPIO_BOTH_EDGES in arch/arm/mach-pxa/viper.c. You could probably just
> make that one edge or the other, or even try for level triggered.
> 
The PXA doesn't have anything like level triggered interrupts on
GPIOs! You should set up the ISP1161 interrupt output as level
triggered, so there won't be any pulses too short for any PXA
processor to recognise. The PXA interrupt should be programmed to
detect the active edge of the interrupt output (and _only_ that).

In the interrupt handler you should make sure, that the interrupt
output of the chip is deactivated by masking all interrupts and
reenable interrupts before exiting the handler. This way you won't
miss any interrupts.
When a new interrupt condition is raised while handling an interrupt
you will either see it in the interrupt status register and can serve
it directly, or it will trigger a new interrupt when reenabling
interrupts at the end of the handler.



Lothar Wassmann


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