Hi Lothar,
Please find below the patch, which adds isp116x-specific
stuff to your ohci-1362.h. Apply it AFTER you have Lindented
your file.
A new macro CHIP_TYPE must now be defined. I added a chip
type field to the ISP1362_REG definition so that with
debugging on, HC_ISP1362_WRITE_ADDR will catch attempts to
access reserved registers for a given chip.
Olav
--- linux-2.6.8.1-isp1362-tmp0/drivers/usb/host/ohci-isp1362.h 2004-09-16
13:30:20.000000000 +0300
+++ linux-2.6.8.1-isp1362-last/drivers/usb/host/ohci-isp1362.h 2004-09-16
13:45:31.000000000 +0300
@@ -33,18 +33,22 @@
#define REG_ACCESS_M 0x800 // reg needs to be merged with shadow reg
#define REG_ACCESS_MASK 0x600
+#define CHIP_TYPE_ISP1362 0x1000
+#define CHIP_TYPE_ISP116x 0x2000
+#define CHIP_TYPE_MASK 0x3000
+
#define ISP1362_BUF_SIZE 4096
#define ISP1362_REG_WRITE_OFFSET 0x80
#ifdef DEBUG
typedef const unsigned int isp1362_reg_t;
#define _BUG_ON(x) BUG_ON(x)
-#define ISP1362_REG(name,addr,width,rw) \
-static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw));
+#define ISP1362_REG(name,addr,width,rw,chip) \
+static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw) | (chip));
#else
typedef const unsigned char isp1362_reg_t;
#define _BUG_ON(x) do {} while(0)
-#define ISP1362_REG(name,addr,width,rw) \
+#define ISP1362_REG(name,addr,width,rw,chip) \
static isp1362_reg_t ISP1362_REG_##name = addr;
#endif
@@ -56,31 +60,50 @@ static isp1362_reg_t ISP1362_REG_##name
* are not defined in the ISP1362 controller register.
* Those registers have to be read/written with the ohci_{read|write}_masked()
functions.
* Bitmasks for the individual bits of these registers are defined in "ohci.h"
+ *
+ * ISP116x implements exactly the same bits as ISP1362
+ * in these registers.
*/
-ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R);
-ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M);
+ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define ISP1362_MASK_HCCONTROL (OHCI_CTRL_HCFS | OHCI_CTRL_RWE | OHCI_CTRL_RWC)
-ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M);
+ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define ISP1362_MASK_HCCMDSTAT (OHCI_HCR | OHCI_SOC)
-ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M);
+ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define ISP1362_MASK_HCINTSTAT (OHCI_INTR_SO | OHCI_INTR_SF | OHCI_INTR_RD |
OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC)
-ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M);
+ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define ISP1362_MASK_HCINTENB (ISP1362_MASK_HCINTSTAT | OHCI_INTR_MIE)
-ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M);
+ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW | REG_ACCESS_M,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
// OHCI_INTR_SF is required for internal housekeeping and shouldn't be disabled by
OHCI layer
#define ISP1362_MASK_HCINTDIS (ISP1362_MASK_HCINTENB & ~OHCI_INTR_SF)
-ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW);
+ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
// Philips ISP1362 specific registers
-ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCHWCFG_DISABLE_SUSPEND (1 << 15)
#define HCHWCFG_GLOBAL_PWRDOWN (1 << 14)
#define HCHWCFG_PULLDOWN_DS1 (1 << 13)
@@ -98,7 +121,11 @@ ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16,
#define HCHWCFG_INT_TRIGGER (1 << 1)
#define HCHWCFG_INT_ENABLE (1 << 0)
-ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW);
+#define HCHWCFG_ISP116x_RESERVED 0xe200 // 116x
+#define HCHWCFG_15KRSEL (1 << 12) // 116x
+
+ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCDMACFG_CTR_ENABLE (1 << 7)
#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
@@ -115,9 +142,15 @@ ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16
#define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4)
#define HCDMACFG_DMA_RW_SELECT (1 << 0)
-ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW);
+#define HCDMACFG_ISP116x_RESERVED 0xff88 // 116x
+#define HCDMACFG_CTR_SEL (1 << 2) // 116x
+#define HCDMACFG_ITLATL_SEL (1 << 1) // 116x
+
+ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
-ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCuPINT_SOF (1 << 0)
#define HCuPINT_ISTL0 (1 << 1)
#define HCuPINT_ISTL1 (1 << 2)
@@ -127,21 +160,36 @@ ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16,
#define HCuPINT_CLKRDY (1 << 6)
#define HCuPINT_INTL (1 << 7)
#define HCuPINT_ATL (1 << 8)
-#define HCuPINT_OTG (1 << 9)
+#define HCuPINT_OTG (1 << 9)
-ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW);
+#define HCuPINT_ISP116x_RESERVED 0xff88 // 116x
+#define HCuPINT_ISP116x_AIIEOT (1 << 2) // 116x
+#define HCuPINT_ISP116x_ATL (1 << 1) // 116x
+
+ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
// same bit definitions apply as for HCuPINT
+#define HCuPINTENB_ISP116x_RESERVED HCuPINT_ISP116x_RESERVED // 116x
-ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R);
+ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCCHIPID_MASK 0xff00
#define HCCHIPID_MAGIC 0x3600
+#define HCCHIPID_ISP116x_MAGIC 0x6100 // 116x
-ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
-ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W);
+ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCSWRES_MAGIC 0x00f6
-ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCITLBUFLEN, 0x2a, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP116x);
// 116x
+
+ISP1362_REG(HCATLBUFLEN, 0x2b, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP116x);
// 116x
+
+ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
#define HCBUFSTAT_ISTL0_FULL (1 << 0)
#define HCBUFSTAT_ISTL1_FULL (1 << 1)
#define HCBUFSTAT_INTL_ACTIVE (1 << 2)
@@ -153,38 +201,52 @@ ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_1
#define HCBUFSTAT_ISTL1_DONE (1 << 9)
#define HCBUFSTAT_PAIRED_PTDPP (1 << 10)
-ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW);
+#define HCBUFSTAT_ISP116x_RESERVED 0xffc0 // 116x
+#define HCBUFSTAT_ISP116x_ITL0_FULL (1 << 0) // 116x
+#define HCBUFSTAT_ISP116x_ITL1_FULL (1 << 1) // 116x
+#define HCBUFSTAT_ISP116x_ATL_FULL (1 << 2) // 116x
+#define HCBUFSTAT_ISP116x_ITL0_DONE (1 << 3) // 116x
+#define HCBUFSTAT_ISP116x_ITL1_DONE (1 << 4) // 116x
+#define HCBUFSTAT_ISP116x_ATL_DONE (1 << 5) // 116x
+
+ISP1362_REG(HCRDITL0LEN, 0x2d, REG_WIDTH_16, REG_ACCESS_R, CHIP_TYPE_ISP116x); // 116x
+
+ISP1362_REG(HCRDITL1LEN, 0x2e, REG_WIDTH_16, REG_ACCESS_R, CHIP_TYPE_ISP116x); // 116x
+
+ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
#define _HCDIRADDR_ADDR Fld(16, 0)
#define HCDIRADDR_ADDR_MASK FMsk(_HCDIRADDR_ADDR)
#define HCDIRADDR_ADDR(n) (FInsrt(n, _HCDIRADDR_ADDR) & FMsk(_HCDIRADDR_ADDR))
#define _HCDIRADDR_COUNT Fld(16, 16)
#define HCDIRADDR_COUNT_MASK FMsk(_HCDIRADDR_COUNT)
#define HCDIRADDR_COUNT(n) (FInsrt(n, _HCDIRADDR_COUNT) & FMsk(_HCDIRADDR_COUNT))
-ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
-ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW);
-
-ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R);
-ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R);
-
-ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R);
-ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW);
-ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R);
+ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW,
+ CHIP_TYPE_ISP1362 | CHIP_TYPE_ISP116x);
+ISP1362_REG(HCATLPORT_ISP116x, 0x41, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP116x);
// 116x
+ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+
+ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R, CHIP_TYPE_ISP1362);
+
+ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R, CHIP_TYPE_ISP1362);
-ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW);
-ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW);
+ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
+ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW, CHIP_TYPE_ISP1362);
/*
* define initial values for the HW configuration registers
@@ -204,6 +266,7 @@ ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_
#define HCDMACFG_INIT_VAL (HCDMACFG_BUF_DIRECT | HCDMACFG_BURST_LEN_4)
#define CAN_USE_32BIT 1
+#define CHIP_TYPE CHIP_TYPE_ISP1362
#else
#error Specify appropriate initialization values for HW configuration registers
@@ -251,6 +314,10 @@ struct ptd {
#define _PTD_LAST_ISO Fld(1, 3)
#define PTD_LAST_ISO(v) FInsrt(v, _PTD_LAST_ISO)
#define PTD_GET_LAST_ISO(p) FExtr((p)->ep_spd, _PTD_LAST_ISO)
+// For 116x, this bit is both for ITL and ATL
+#define _PTD_LAST Fld(1, 3) // 116x
+#define PTD_LAST(v) FInsrt(v, _PTD_LAST_ISO) // 116x
+#define PTD_GET_LAST(p) FExtr((p)->ep_spd, _PTD_LAST_ISO) // 116x
#define _PTD_EP Fld(4, 4)
#define PTD_EP(v) FInsrt(v, _PTD_EP)
#define PTD_GET_EP(p) FExtr((p)->ep_spd, _PTD_EP)
@@ -264,10 +331,15 @@ struct ptd {
#define _PTD_DIR Fld(2, 2)
#define PTD_DIR(v) FInsrt(v, _PTD_DIR)
#define PTD_GET_DIR(p) FExtr((p)->dir, _PTD_DIR)
-
-#define _PTD_FA Fld(7, 0)
-#define PTD_FA(v) FInsrt(v, _PTD_FA)
-#define PTD_GET_FA(p) FExtr((p)->func_addr,_PTD_FA)
+#define _PTD_B5_5 Fld(1, 5) // 116x
+#define PTD_B5_5(v) FInsrt(v, _PTD_B5_5) // 116x
+#define PTD_GET_B5_5(p) FExtr((p)->dir, _PTD_B5_5) // 116x
+#define _PTD_FA Fld(7, 0)
+#define PTD_FA(v) FInsrt(v, _PTD_FA)
+#define PTD_GET_FA(p) FExtr((p)->func_addr,_PTD_FA)
+#define _PTD_FMT Fld(1, 7) // 116x
+#define PTD_FMT(v) FInsrt(v, _PTD_FMT) // 116x
+#define PTD_GET_FMT(p) FExtr((p)->func_addr,_PTD_FMT) // 116x
#define _PTD_SF Fld(4, 0)
#define PTD_SF(v) FInsrt(v, _PTD_SF)
@@ -369,6 +441,7 @@ static inline void HC_ISP1362_WRITE_ADDR
{
//DDPRINTK("A>[EMAIL PROTECTED]", reg, (u32)hc_isp1362_addr_reg);
_BUG_ON((reg & ISP1362_REG_WRITE_OFFSET) && !(reg & REG_ACCESS_W));
+ _BUG_ON(!(reg & CHIP_TYPE));
_BUG_ON(!irqs_disabled());
writew(reg, hc_isp1362_addr_reg);
}
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