Hi,

> So, I ignored the error with the CLKRDY pin, but now I'm getting
> two problems:
> 1a. I'm getting failed memory checks 
> 1b. I'm triggering the _WARN_ON statements regarding HCuPINT_EOT at
> the end of write_buffer (which I'm assuming is the cause of 1a)
>
Yes. This is a sure sign that write instructions complete before the
actual write to the device has taken place. The last writes to the
fifo are still outstanding when the read of the status register is
performed, thus it reports that not all data has been transferred.

This also means that the delay function that should guarantee the
minimum time between writing the addr reg and accessing the data reg
will complete before the actual write to the addr reg has taken
place.

How did you implement the delay function?

What is your system architecture?

> 2. I'm getting 'irq24: nobody cared', which I'm assuming is because
> the driver has enabled interrupts on the chip before the driver has
> actually requested the IRQ.  (This may be caused by the above
> error)
> 
> My guess is I'm having trouble with the new write_buffer /
> write_fifo (as it uses writesl / writesw instead of its own loop). 
> I'm going to go on this assumption (and ignore CLKRDY completely),
> unless anyone else runs into this problem or has a good idea.
>
Unless you have a memory controller that cannot accomodate the data
reg access timing so that you need additional delays between each
access that should not be a problem.
The crucial point is the delay between writing the addr reg and
accessing the data reg. This delay of 300ns/462ns most probably cannot
be accomplished with the setup of the memory controller alone.


Lothar Wassmann


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