Johan Hovold <jo...@kernel.org> 於 2019年7月16日 週二 下午4:49寫道：
> > #define PL2303_FLOWCTRL_MASK 0xf0
> > +#define PL2303_HXN_FLOWCTRL_MASK 0x1C
> > +#define PL2303_HXN_FLOWCTRL 0x0A
>
> I asked you to keep related defines together (and to move the mask where
> the register define was, not the other way round). Please move these to
> the other HXN defines below, and keep the register address defines
> before the corresponding bit defines.
Charles Ans:
I am not 100% sure what you mean, please see if it is defined below
#define PL2303_FLOWCTRL_MASK 0xf0
#define PL2303_READ_TYPE_HX_STATUS 0x8080
#define PL2303_HXN_CTRL_XON_XOFF 0x0C
#define PL2303_HXN_CTRL_RTS_CTS 0x18
#define PL2303_HXN_CTRL_NONE 0x1C
#define PL2303_HXN_FLOWCTRL_MASK 0x1C
#define PL2303_HXN_FLOWCTRL 0x0A
#define PL2303_HXN_RESET_UP_DOWNSTREAM_DATA_PIPE 0x03
#define PL2303_HXN_RESET_UP_DOWNSTREAM_DATA_PIPE_MASK 0x03
#define PL2303_HXN_RESET_CONTROL 0x07
> > +
> > +#define PL2303_HXN_RESET_CONTROL_MASK 0x03
> This makes no sense. The whole register is used for reset. If you want a
> define that can be used for resetting both pipes then add two separate
> defines for up and down respectively, and add a third define for
> resetting both buffer as a bitwise OR of the two.
Charles Ans:
Yes,The whole register is used for reset.
Bit 0 and bit 1 are used for up & downstream data pipe,
Bit 2 for interface reset
Bit 4 for chip reset.
But I only reset bit 0 & bit 1.
> Also move this one after the corresponding register address define
> below.
>
> > +#define PL2303_HXN_RESET_CONTROL 0x07
> > +#define PL2303_HXN_CTRL_XON_XOFF 0x0C
> > +#define PL2303_HXN_CTRL_RTS_CTS 0x18
> > +#define PL2303_HXN_CTRL_NONE 0x1C
Charles Ans:
I am not 100% sure what you mean, please see if it is defined below
#define PL2303_FLOWCTRL_MASK 0xf0
#define PL2303_READ_TYPE_HX_STATUS 0x8080
#define PL2303_HXN_CTRL_XON_XOFF 0x0C
#define PL2303_HXN_CTRL_RTS_CTS 0x18
#define PL2303_HXN_CTRL_NONE 0x1C
#define PL2303_HXN_FLOWCTRL_MASK 0x1C
#define PL2303_HXN_FLOWCTRL 0x0A
#define PL2303_HXN_RESET_UP_DOWNSTREAM_DATA_PIPE 0x03
#define PL2303_HXN_RESET_UP_DOWNSTREAM_DATA_PIPE_MASK 0x03
#define PL2303_HXN_RESET_CONTROL 0x07
> > + } else if (spriv->type == &pl2303_type_data[TYPE_HXN]) {
> > /* reset upstream data pipes */
>
> This comment belongs in the last else block. Your new code shouldn't
> need one.
Charles Ans:
OK, I will remove this comment.
>
> > + pl2303_update_reg(serial, PL2303_HXN_RESET_CONTROL,
> > + PL2303_HXN_RESET_CONTROL_MASK, 0x03);
>
> So two things; first, do you really need to read back the current value?
> I would assume that it always reads back as 0 and that writing 0x03 in
> this case would be sufficient to reset both buffers.
>
Charles Ans:
Yes, I want to read back the current value.
because the whole register is used for reset.
Bit 0 and bit 1 are used for up & downstream data pipe,
Bit 2 for interface reset
Bit 4 for chip reset.
But I only reset bit 0 & bit 1.
> Second, please use a define for 0x03; no magic constants, as we have
> discussed before. You don't need a separate mask define if you're always
> resetting both buffers together (just use the same value define twice).
Charles Ans:
OK, I will define for 0x03.
#define PL2303_HXN_RESET_UP_DOWNSTREAM_DATA_PIPE 0x03
Charles Yeh.
