Johan Hovold <jo...@kernel.org> 於 2019年9月23日 週一 下午6:24寫道： > That looks much better. But please move the reset defines above the > flow control ones to keep the registers sorted by address (0x7 < 0xa).
Thank you for your reply Charles Ans: The new define is follows #define PL2303_READ_TYPE_HX_STATUS 0x8080 #define PL2303_HXN_RESET_REG 0x07 #define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 #define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 #define PL2303_HXN_FLOWCTRL_REG 0x0A #define PL2303_HXN_FLOWCTRL_MASK 0x1C #define PL2303_HXN_FLOWCTRL_NONE 0x1C #define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 #define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0C > Also looks good, thanks. Just move the reset define block as mentioned > above. Thank you for your reply Please confirm the above new define If there is no problem.. I will write a new Patch file. Charles.
