On 9/14/06, Michael Galassi <[EMAIL PROTECTED]> wrote:
> It is also worth noting that as released in MVL pro 4.0.1 it only
> supports hard_temac 1.00.a and plb_temac 2.00.a, both of which are
> tagged as deprecated in the current version (8.2.01i) of Xilinx's
> EDK. The current version of {plb,hard}_temac (3.00.a) goes to great
> lengths to break compatibility with older versions. This will
> presumably be fixed next month when it is rumored that wonderful new
> things will come from Xilinx. In the mean-time it is possible, though
> neither simple, nor fun, to create Virtex4 designs with the older IP.
So what direction do we (as the community) want to go for supporting
Xilinx IP in the Linux kernel?
IIRC, Xilinx intends to get drivers submitted into mainline. (Based
on their cross-platform driver support code). It is unknown which and
how many drivers for different IP versions will be submitted.
However, the xilinx driver code is verbose and does not match well
with the rest of the Linux code base. (due to the cross platform
support) Plus, the Xilinx tool work flow is geared towards the EDK
tool overwriting the driver code in the kernel tree with code for the
generated design. In which case, does it even make sense to accept
Xilinx drivers into the Linux tree when they are just going to get
overwritten by the toolchain anyway? Unfortunately, regenerating
drivers has it's own problems considering that the license on the
generated code is not GPL compatible at the moment.
If we reject the Xilinx driver code, then we either have to do without
Xilinx support in mainline, or we need to write new drivers that
address the above issues (support multiple IP versions, etc). The
Xilinx support in mainline right now does not use any Xilinx code.
(Xilinx PIC and UART).
Thoughts?
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
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