Hi, Luigi: I am really thankful for your nice suggestions. 1. The delay for pps cable to calnex is already compensated in calnex configuration. 2. Yes, RX and TX path are asymmetry. the calnex can measure the T1, T4 and 2way time error, those time errors are only a few nano seconds, that means correct delays are compensated. https://www.calnexsol.cn/docman/techlib/timing-and-sync-lab/40-interpretation-of-time-error-results/file 3. the 1PPS is driven by zarlink z30772 DPLL. I will check whether is there any reclocking logic.
Thanks Alex Luigi 'Comio' Mantellini <luigi.mantell...@gmail.com> 于2022年9月8日周四 19:57写道： > Hi Alex, > > some guile line that I follow during my debug sessions: > > - Are you using a good cable-delay estimation for your cable? (Consider > ~5ns/m for classical eth cables) I suggest you to physically measure the > delay and place it as Dcable cell in Calnex configuration. > - Have you checked about any asymmetry between RX and TX paths? Can you > short-circuit your timestamper to check? You need to ask your FPGA and HW > experts. > - How is the 1PPS driven? Is there any reclocking logic? You need to ask > your FPGA-experts. > > > ciao > > luigi > > > Il giorno gio 8 set 2022 alle ore 13:44 Hamilton Alex < > alexzanda...@gmail.com> ha scritto: > >> Hi: >> I got an issue that linuxptp result doesn't match 1PPS measurement. >> my board is acting as a slave, the calnex is acting as a master with >> reference clock. >> after ptp4l runs, result is below, looks pretty good: >> >> ptp4l[130166.661]: rms 1 max 2 freq -50 +/- 4 delay 9059 +/- >> 0 >> ptp4l[130167.661]: rms 1 max 1 freq -50 +/- 2 delay 9058 +/- >> 0 >> ptp4l[130168.662]: rms 1 max 2 freq -52 +/- 3 delay 9058 +/- >> 1 >> ptp4l[130169.661]: rms 1 max 3 freq -49 +/- 4 delay 9058 +/- >> 0 >> ptp4l[130170.661]: rms 1 max 2 freq -50 +/- 4 delay 9059 +/- >> 0 >> ptp4l[130171.662]: rms 1 max 2 freq -49 +/- 3 delay 9058 +/- >> 0 >> >> my board has 1PPS output, I connect it to the master and compared with >> reference PPS. >> however, the 1pps time error is around 40 NS, which means my board is >> ahead of the reference for about 40NS, which doesn't match the result >> dumped by ptp4l. >> >> anyone has met similar issue before? how to debug such issue? >> >> - >> >> 1ppsTE = (T1ppsMeasIngress – Dcable) - TRef >> >> >> https://calnexsolutions.atlassian.net/wiki/spaces/KB/pages/71991334/T-BC+Time+Error+Metrics >> >> Thanks >> Alex >> >> _______________________________________________ >> Linuxptp-devel mailing list >> Linuxptp-devel@lists.sourceforge.net >> https://lists.sourceforge.net/lists/listinfo/linuxptp-devel >> > > > -- > *Luigi 'Comio' Mantellini* > My Professional Profile <http://www.linkedin.com/in/comio> > > *"UNIX is very simple, it just needs a genius to understand its > simplicity." [cit.]* > >
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