Hi, Richard: I am not quite understand. I am using Calnex master-->board slave, if the linuxptp print out is correct, that means local clock has the same frequency and phase as master clock, then the 1PPS out should near the reference 1PPS.
why path asymmetry would affect the 1PPS out? Thanks Alex Richard Cochran <richardcoch...@gmail.com> 于2022年9月8日周四 21:40写道： > On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote: > > > however, the 1pps time error is around 40 NS, which means my board is > > ahead of the reference for about 40NS, which doesn't match the result > > dumped by ptp4l. > > > > anyone has met similar issue before? how to debug such issue? > > This is likely due to path asymmetry. > > HTH, > Richard >
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