llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-selectiondag
Author: Iris Shi (el-ev)
<details>
<summary>Changes</summary>
Drop the `Lo.isMinValue()` check in `lowerRangeToAssertZExt`.
The check was introduced in 2bba779272a2 when the bit width was computed via
`logBase2(Hi)`, which required `Lo == 0` for correctness. It is no longer
needed since 9e04befb0979 when we switched to
`getUnsignedMax().getActiveBits()` for bit width.
The change in `DAGCombiner.cpp` is to prevent a regression in
`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll`. I wasn't able to
construct an individual test for it.
---
Full diff: https://github.com/llvm/llvm-project/pull/196785.diff
3 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (-4)
- (modified) llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll (+3-3)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT())
return N0;
+ // fold (assert?ext c, vt) -> c
+ if (isa<ConstantSDNode>(N0))
+ return N0;
+
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
N0.getOperand(0).getOpcode() == Opcode) {
// We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
return Op;
- APInt Lo = CR->getUnsignedMin();
- if (!Lo.isMinValue())
- return Op;
-
APInt Hi = CR->getUnsignedMax();
unsigned Bits = std::max(Hi.getActiveBits(),
static_cast<unsigned>(IntegerType::MIN_INT_BITS));
diff --git a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
index ad26dfa7f93e8..a8be7e5827af0 100644
--- a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+++ b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
@@ -11,7 +11,7 @@ define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64
range(i64 0, 4294967296) %
; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mov_b32_e32 v1, v3
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2
; CHECK-NEXT: s_setpc_b64 s[30:31]
%xor = xor i64 %arg0, %arg1
@@ -24,7 +24,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64
range(i64 0, 4294967296) %a
; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mov_b32_e32 v1, v3
; CHECK-NEXT: v_or_b32_e32 v0, v0, v2
; CHECK-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %arg0, %arg1
@@ -50,7 +50,7 @@ define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64
0, 65) inreg %arg)
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_not_b64 s[4:5], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v0, s4
-; CHECK-NEXT: v_mov_b32_e32 v1, s5
+; CHECK-NEXT: v_mov_b32_e32 v1, -1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%xor = xor i64 %arg, -1
ret i64 %xor
``````````
</details>
https://github.com/llvm/llvm-project/pull/196785
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