From: Austin Hu <austin...@intel.com>
For the HDMI extended mode issue, when setting CRTC base for PIPE B, the
Display B/Sprite Linear Offset Register
isn't never updated by the panning offset on MDFLD, so that HDMI's upper left
coordinate is always (0, 0).
Fixed it by updating the DSPBLINOFF register with the correct offset.
Signed-off-by: Austin Hu <austin...@intel.com>
Signed-off-by: Jackie Li <yaodong...@intel.com>
Signed-off-by: Hitesh K. Patel <hitesh.k.pa...@intel.com>
---
drivers/staging/mrst/drv/psb_intel_display2.c | 18 ++++++++----------
1 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c
b/drivers/staging/mrst/drv/psb_intel_display2.c
index de18bd4..bcdda91 100644
--- a/drivers/staging/mrst/drv/psb_intel_display2.c
+++ b/drivers/staging/mrst/drv/psb_intel_display2.c
@@ -345,7 +345,7 @@ int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int
x, int y, struct drm_f
struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
int pipe = psb_intel_crtc->pipe;
unsigned long Start, Offset;
- int dspbase = DSPABASE;
+ int dsplinoff = DSPALINOFF;
int dspsurf = DSPASURF;
int dspstride = DSPASTRIDE;
int dspcntr_reg = DSPACNTR;
@@ -365,18 +365,16 @@ int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int
x, int y, struct drm_f
switch (pipe) {
case 0:
if (IS_MID(dev))
- dspbase = DSPALINOFF;
+ dsplinoff = DSPALINOFF;
break;
case 1:
- dspbase = DSPBBASE;
+ dsplinoff = DSPBLINOFF;
dspsurf = DSPBSURF;
dspstride = DSPBSTRIDE;
dspcntr_reg = DSPBCNTR;
- if (IS_MDFLD(dev))
- dspbase = MRST_DSPBBASE;
break;
case 2:
- dspbase = DSPCBASE;
+ dsplinoff = DSPCLINOFF;
dspsurf = DSPCSURF;
dspstride = DSPCSTRIDE;
dspcntr_reg = DSPCCNTR;
@@ -421,13 +419,13 @@ int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int
x, int y, struct drm_f
PSB_DEBUG_ENTRY("Writing base %08lX %08lX %d %d\n", Start, Offset, x,
y);
if (IS_I965G(dev) || IS_MID(dev)) {
- REG_WRITE(dspbase, Offset);
- REG_READ(dspbase);
+ REG_WRITE(dsplinoff, Offset);
+ REG_READ(dsplinoff);
REG_WRITE(dspsurf, Start);
REG_READ(dspsurf);
} else {
- REG_WRITE(dspbase, Start + Offset);
- REG_READ(dspbase);
+ REG_WRITE(dsplinoff, Start + Offset);
+ REG_READ(dsplinoff);
}
psb_intel_pipe_set_base_exit:
--
1.7.1
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