From: Li Zeng <li.z...@intel.com>
1. Optimize GL3 invalidation for video, only invalidates
when flush msvdx/topaz mmu cache
2. Modify GL3 register value, clean bit GL3_IGN_VEC_HINT
3. Modify GFX OSPM code to avoid power-off
GL3 island because video is still using GL3, this is a
work around before we get a idea on how to power-off GL3
Signed-off-by: Li Zeng <li.z...@intel.com>
Signed-off-by: Hitesh K. Patel <hitesh.k.pa...@intel.com>
---
drivers/staging/mrst/drv/mdfld_gl3.h | 2 +-
drivers/staging/mrst/drv/psb_powermgmt.c | 22 ++++++++++++++++------
drivers/staging/mrst/drv/psb_reg.h | 1 +
drivers/staging/mrst/drv/psb_sgx.c | 15 ++++++++-------
drivers/staging/mrst/imgv/pnw_topaz.c | 2 --
drivers/staging/mrst/imgv/pnw_topazinit.c | 1 +
drivers/staging/mrst/imgv/psb_msvdx.c | 3 +--
7 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/mrst/drv/mdfld_gl3.h
b/drivers/staging/mrst/drv/mdfld_gl3.h
index 35f9e34..02bdf54 100644
--- a/drivers/staging/mrst/drv/mdfld_gl3.h
+++ b/drivers/staging/mrst/drv/mdfld_gl3.h
@@ -102,7 +102,7 @@
#define MDFLD_GL3_ENABLE_CACHE (MDFLD_GL3_BYP_PREQ2_USSE3 |
MDLFD_GL3_BYP_PREQ2_USSE2 | \
MDFLD_GL3_BYP_PREQ1_USE1 | MDFLD_GL3_BYP_PREQ1_USE0 |
MDFLD_GL3_BYP_PREQ1_ISPZ | \
MDFLD_GL3_BYP_PREQ1_PBE | MDFLD_GL3_BYP_PREQ1_VDM |
MDFLD_GL3_BYP_PREQ1_TA | \
- MDFLD_GL3_BYP_PREQ1_MMU | MDFLD_GL3_IGN_VEC_HINT)
+ MDFLD_GL3_BYP_PREQ1_MMU)
#define MDFLD_GL3_INVALIDATE_CACHE (MDFLD_GL3_ENABLE_CACHE |
MDFLD_GL3_INVALIDATE)
diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c
b/drivers/staging/mrst/drv/psb_powermgmt.c
index b6765db..8c50579 100644
--- a/drivers/staging/mrst/drv/psb_powermgmt.c
+++ b/drivers/staging/mrst/drv/psb_powermgmt.c
@@ -1684,12 +1684,22 @@ void ospm_power_island_up(int hw_islands)
#endif
}
if (hw_islands & OSPM_VIDEO_ENC_ISLAND) {
- pwr_cnt &= ~PSB_PWRGT_VID_ENC_MASK;
- pwr_mask |= PSB_PWRGT_VID_ENC_MASK;
+ if (IS_MDFLD(gpDrmDevice) && dev_priv->platform_rev_id
!= MDFLD_PNW_A0) {
+ pwr_cnt &= ~(PSB_PWRGT_VID_ENC_MASK |
PSB_PWRGT_GL3_MASK);
+ pwr_mask |= (PSB_PWRGT_VID_ENC_MASK |
PSB_PWRGT_GL3_MASK);
+ } else {
+ pwr_cnt &= ~PSB_PWRGT_VID_ENC_MASK;
+ pwr_mask |= PSB_PWRGT_VID_ENC_MASK;
+ }
}
if (hw_islands & OSPM_VIDEO_DEC_ISLAND) {
- pwr_cnt &= ~PSB_PWRGT_VID_DEC_MASK;
- pwr_mask |= PSB_PWRGT_VID_DEC_MASK;
+ if (IS_MDFLD(gpDrmDevice) && dev_priv->platform_rev_id
!= MDFLD_PNW_A0) {
+ pwr_cnt &= ~(PSB_PWRGT_VID_DEC_MASK |
PSB_PWRGT_GL3_MASK);
+ pwr_mask |= (PSB_PWRGT_VID_DEC_MASK |
PSB_PWRGT_GL3_MASK);
+ } else {
+ pwr_cnt &= ~PSB_PWRGT_VID_DEC_MASK;
+ pwr_mask |= PSB_PWRGT_VID_DEC_MASK;
+ }
}
outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
@@ -1786,8 +1796,8 @@ void ospm_power_island_down(int islands)
if (islands & OSPM_GRAPHICS_ISLAND) {
if (IS_MDFLD(gpDrmDevice) && dev_priv->platform_rev_id !=
MDFLD_PNW_A0) {
- pwr_cnt |= PSB_PWRGT_GFX_MASK_B0;
- pwr_mask |= PSB_PWRGT_GFX_MASK_B0;
+ pwr_cnt |= PSB_PWRGT_GFX_MASK;
+ pwr_mask |= PSB_PWRGT_GFX_MASK;
} else {
pwr_cnt |= PSB_PWRGT_GFX_MASK;
pwr_mask |= PSB_PWRGT_GFX_MASK;
diff --git a/drivers/staging/mrst/drv/psb_reg.h
b/drivers/staging/mrst/drv/psb_reg.h
index 0c110c2..cbe5405 100644
--- a/drivers/staging/mrst/drv/psb_reg.h
+++ b/drivers/staging/mrst/drv/psb_reg.h
@@ -563,6 +563,7 @@
#define PSB_APM_STS 0x04
#define PSB_PWRGT_VID_ENC_MASK 0x30
#define PSB_PWRGT_VID_DEC_MASK 0xc
+#define PSB_PWRGT_GL3_MASK 0xc0
#define PSB_PM_SSC 0x20
#define PSB_PM_SSS 0x30
diff --git a/drivers/staging/mrst/drv/psb_sgx.c
b/drivers/staging/mrst/drv/psb_sgx.c
index 563c65c..fdb164f 100644
--- a/drivers/staging/mrst/drv/psb_sgx.c
+++ b/drivers/staging/mrst/drv/psb_sgx.c
@@ -330,11 +330,11 @@ static int psb_validate_buffer_list(struct drm_file
*file_priv,
placement.num_busy_placement = 0;
placement.fpfn = 0;
placement.lpfn = 0;
-
+ /*
ret = ttm_bo_validate(bo, &placement, 1, 0, 0);
if (unlikely(ret != 0))
goto out_err;
-
+ */
fence_types |= cur_fence_type;
entry->new_sync_obj_arg = (void *)
(unsigned long) cur_fence_type;
@@ -955,21 +955,22 @@ void psb_gl3_global_invalidation(struct drm_device *dev)
{
#ifdef CONFIG_MDFD_GL3
struct drm_psb_private *dev_priv = dev->dev_private;
- uint32_t gl3_ctl, gl3_stat, poll_count = 0x1000;
+ uint32_t gl3_ctl;
+ /* uint32_t poll_count = 0x1000, gl3_stat; */
/* IS there a way to avoid multiple invalidation simultaneously? Maybe
a ATOM value */
gl3_ctl = PSB_RVDC32(PSB_GL3_CACHE_CTL);
- //gl3_ctl = PSB_RVDC32(0xb0000);
- //printk("GCL_CR_CTL2 is 0x%08x\n", gl3_ctl);
+ /* gl3_ctl = PSB_RVDC32(0xb0000); */
+ /* printk("gl3_invalidation: GCL_CR_CTL2 is 0x%08x\n", gl3_ctl); */
PSB_WVDC32(gl3_ctl | 0x2, PSB_GL3_CACHE_CTL);
+#if 0
while(poll_count) {
gl3_stat = PSB_RVDC32(PSB_GL3_CACHE_STAT);
if(gl3_stat & 0x1) {
PSB_WVDC32(gl3_stat | 0x1, PSB_GL3_CACHE_STAT); /*
Frome D.Will : write 1 to Inval_done bit to clear it */
- //return 0;
return;
}
cpu_relax();
@@ -977,6 +978,6 @@ void psb_gl3_global_invalidation(struct drm_device *dev)
}
DRM_ERROR("Invalidation GL3 timeout\n");
- //return -1;
+#endif
#endif
}
diff --git a/drivers/staging/mrst/imgv/pnw_topaz.c
b/drivers/staging/mrst/imgv/pnw_topaz.c
index 3f884a5..5795bf8 100644
--- a/drivers/staging/mrst/imgv/pnw_topaz.c
+++ b/drivers/staging/mrst/imgv/pnw_topaz.c
@@ -428,8 +428,6 @@ pnw_topaz_send(struct drm_device *dev, void *cmd,
PSB_DEBUG_GENERAL("TOPAZ: send the command in the buffer one by one\n");
- psb_gl3_global_invalidation(dev);
-
while (cmd_size > 0) {
cur_cmd_header = (struct topaz_cmd_header *) command;
cur_cmd_id = cur_cmd_header->id;
diff --git a/drivers/staging/mrst/imgv/pnw_topazinit.c
b/drivers/staging/mrst/imgv/pnw_topazinit.c
index 3ce367c..cf6b70a 100644
--- a/drivers/staging/mrst/imgv/pnw_topazinit.c
+++ b/drivers/staging/mrst/imgv/pnw_topazinit.c
@@ -1704,6 +1704,7 @@ void pnw_topaz_mmu_flushcache(struct drm_psb_private
*dev_priv)
mmu_control &= (~F_ENCODE(1, TOPAZ_CR_MMU_INVALDC));
//mmu_control &= (~F_ENCODE(1, TOPAZ_CR_MMU_FLUSH));
TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, mmu_control, 0);
+ psb_gl3_global_invalidation(dev_priv->dev);
}
#if DEBUG_FUNCTION
diff --git a/drivers/staging/mrst/imgv/psb_msvdx.c
b/drivers/staging/mrst/imgv/psb_msvdx.c
index 81f27f2..ea16fb5 100644
--- a/drivers/staging/mrst/imgv/psb_msvdx.c
+++ b/drivers/staging/mrst/imgv/psb_msvdx.c
@@ -129,6 +129,7 @@ static int psb_msvdx_map_command(struct drm_device *dev,
flags = MEMIO_READ_FIELD(cmd,
FW_DEVA_DECODE_FLAGS);
flags |= FW_DEVA_INVALIDATE_MMU;
MEMIO_WRITE_FIELD(cmd,
FW_DEVA_DECODE_FLAGS, flags);
+ psb_gl3_global_invalidation(dev);
}
PSB_DEBUG_GENERAL("MSVDX:Set MMU invalidate\n");
@@ -442,8 +443,6 @@ static int psb_msvdx_send(struct drm_device *dev, void *cmd,
int ret = 0;
struct drm_psb_private *dev_priv = dev->dev_private;
- psb_gl3_global_invalidation(dev);
-
while (cmd_size > 0) {
uint32_t cur_cmd_size = MEMIO_READ_FIELD(cmd, FWRK_GENMSG_SIZE);
uint32_t cur_cmd_id = MEMIO_READ_FIELD(cmd, FWRK_GENMSG_ID);
--
1.7.1
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