>>>c:=a+b
>>>RISC: add a,b,c
>>>CISC: mov a,c (1)
>>> add b,c (2)
>>>
>>>When (2) depends on (1), there is no possibility for parallelization.
>>>Good, you can argue that instructions on 3 operators are better than
>>>the one on 2 instructions.
>>
>>I'm no expert, but isn't this an unfair characterization of CISC?
>
>Yes and no.
All modern processors use a dynamic execution architecture that blends
out-of-order and speculative execution with hardware register renaming and
branch prediction. These processors feature an in-order issue pipeline,
which breaks processor macroinstructions into simple, micro-operations, and
an out-of-order, superscalar processor core, which executes the micro-ops.
The out-of-order core of the processor contains several pipelines to which
integer, branch, floating-point and memory execution units are attached.
Many instructions contain few micro-operations then the processor is able to
execute more than 1 instruction per cycle. Some instructions are complex and
needs several cycles to be executed (div, sqrt, cos, ...) but they are not
often used.
Is that processor a RISC or a CISC ? Neither a RISC nor a CISC! And it is
really faster than a RISC or a CISC.
Yves
