>> (Say, I never heard of any cacheless Celeron chips, or any other
>> cacheless chip since the late eighties...)
>
>
> Eh? All the original Celeron chips were sans cache, only after
>the customers started screaming about a 300 performing like a 200mhz
>pentium did the 300A and later come out with a reduced size cache (instead
>of none).
You're *both* half right.
*ALL* Intel P6 family CPUs (PPro, PII, Celeron, Xeon, PIII) have 32KB Level 1
cache, divided into 16KB of instruction cache and 16KB of data cache. The Level 1
cache always runs at core speed.
Where the products differ is in the amount and speed of the Level 2 cache.
PPro had 256KB, 512KB or 1024KB of L2 cache fabricated into the chip package &
running at core speed. Almost all PPros were the 256KB version, the 512KB version
was extortionately expensive, and the 1024KB version so dear that very few people
ever saw one.
Xeon has 512KB, 1024KB or 2048KB of L2 cache, running at core speed, somewhere in
the Slot 2 cartridge. Probably on seperate chips. +/- the same comments about
pricing apply as to the PPro with half as much L2 cache.
PII and PIII both have 512KB of L2 cache running at half core speed, on a seperate
chip mounted inside the Slot 1 cartridge.
The original Celeron (266 and 300) had no (OKB) L2 cache. These may be repackaged
PII components with duff L2 cache disabled. In any case, they are obsolete, you
can't seem to buy new ones from "normal" retail outlets any more.
Later Celerons (300A, 333 and above) have 128KB of L2 cache, integrated onto the
CPU chip and running at core speed.
I believe that mobile PII processors (the "Tillamook" package, not the Slot 1
cartridge) have only 256KB L2 cache, but running at full core speed. But I don't
claim ever to have seen one.
If you have a BIOS which allows you to mess with the cache settings then you can
experiment. My Supermicro BX chipset motherboard with AMI BIOS allows you to turn
on or off the level 2 cache, and also to enable or disable the ECC mode in the
cache memory (if your CPU supports it - the "Klamath" PIIs, 233/266/300 MHz,
didn't have ECC cache capability).
On a dual PII-350 system, I found (a) having the ECC turned on or off made no
difference at all to any benchmark - reccomendation, if your system supports ECC,
enable it, it costs nothing & should aid reliability; (b) having the L2 cache
disabled slowed the system down by approx. 10% so far as "normal" benchmarks are
concerned, but made little if any difference to the speed of Prime95. There may be
more effect on systems that do not have PC100 SDRAM. This finding is corroborated
by other personal experience, I found that the Celeron 266 system my employers
(stingy so-and-so's) bought for me to use at work ran Prime95 at pretty much the
same speed as my own PII-266, which quite honestly surprised me at the time.
The cache tuning which has been done in Prime95 appears to be aimed to optimizing
the use of the L1 cache, I don't see anything which the L2 cache helps out much.
Corroborative evidence for this comes from my PII-266 system, the Pheonix BIOS on
the Intel LX motherboard on this system allows you to disable L1 and L2 cache (but
not seperately), if you disable the cache then Prime95 runs several times slower!
(This may be the source of the fable about original Celerons being dead slow -
systems integrators turned off the cache in the BIOS, not realizing that the L1
cache was being shut down, too)
The point is that the amount and speed of Level 2 cache, on Intel P6 family CPUs,
appears not to have a large effect in the performance of Prime95 - certainly not
enough to justify paying 10x the price for a Xeon 450 2MB as opposed to a PII-450!
So far as Pentium III is concerned, call me a cynical old f*** if you must, but I
think it's marketing hype. I would have thought that the "signal processing" and
"rendering" type applications, at which the KNI instructions seem to be targeted,
would be better done in dedicated hardware outside the CPU. After all, it
isn't the CPU that connects to the Internet, it's the modem or network adapter
- and what you see on the screen is an image of the contents of the memory in the
graphics adapter. Sorry, Intel, but Katmai looks more like a version upgrade (in a
strange direction) than a quantum leap in technology. Nevertheless, no doubt, lots
of people with newish PII systems and more money than sense will upgrade to a PIII
with little increase in clock speed - which means there may shortly be a surplus
of second-user PII CPUs on the market at ridiculously low prices. Cheap upgrades
for some of us? (Check that the idiot who had the CPU before you didn't put his
thumb through the fragile fan housing when he was removing the cartridge from its
mounting!)
Now, if what we read about the forthcoming AMD K7 is true (256KB L1 cache, FPU
capable of executing 2 double-precision operations per clock, bus speeds 133MHz
initially, 200 MHz later), then that might make a *real* impact on Mersenne number
testing - even if we do need to re-optimize to take full advantage of it.
Regards
Brian Beesley
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