RE: Mersenne: Pentium III

[Paul Derbyshire]

>...minimize possible cache hits on cacheless Celeron chips...

Isn't that a vacuous statement? :-)

(Say, I never heard of any cacheless Celeron chips, or any other
 cacheless chip since the late eighties...)


-- 
   .*.  "Clouds are not spheres, mountains are not cones, coastlines are not
-()  <  circles, and bark is not smooth, nor does lightning travel in a
   `*'  straight line."    -------------------------------------------------
        -- B. Mandelbrot  |http://surf.to/pgd.net
_____________________ ____|________     Paul Derbyshire     [EMAIL PROTECTED]
Programmer & Humanist|ICQ: 10423848|
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