> >...minimize possible cache hits on cacheless Celeron chips...
>
> Isn't that a vacuous statement? :-)
>
> (Say, I never heard of any cacheless Celeron chips, or any other
> cacheless chip since the late eighties...)
It is a bit confusing, yes? :-)
I'm referring to the L2 cache, for which the first Celerons had none. You
can get Celeron's now with 128k (or maybe 256k also?) now. Those ones have
the distinct advantage that the L2 cache runs at CPU speed, not CPU/2 speed
like the PII/Xeon/etc.
By keeping the code small, you'll hope to keep the program's main bits in
the L1 cache.
BTW, here's the press release URL I got from Intel today:
http://www.intel.com/tech/work/desktop/unleash.htm?iid=mail+tw11&
You'll notice that it *does* mention an improvement in FPU speeds due to the
addition of a 3rd register, enhancing parallel instruction execution, making
the PIII capable of 4 floating point instructions in a single instruction.
That oughta help Prime95, yes?
Plus, seperate registers now for FP and MMX means better performance when
you're actually doing other stuff on the machine, like playing a game or
whatever, since it won't have to store the registry, then swap back in
later.
Plus, you could use the SIMD stuff to *specifically* load stuff into the L2
cache ahead of time, so when the code needs it, it'll be waiting in the fast
ram for ya. Smaller improvement than the FPU stuff, but could be a few
percent. Not bad.
And of course, when it hits 600MHz, that'll be pretty nice too.
Aaron
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