From: Nicolai Hähnle <nicolai.haeh...@amd.com>
v2: update for LLVMValueRefs in ac_shader_abi
---
src/amd/common/ac_nir_to_llvm.c | 10 ++++------
src/amd/common/ac_shader_abi.h | 2 ++
src/gallium/drivers/radeonsi/si_shader.c | 6 ++++--
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 6ba03cf..0cd3590 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -121,22 +121,20 @@ struct nir_to_llvm_context {
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring;
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef prim_mask;
LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
- LLVMValueRef ancillary;
- LLVMValueRef sample_coverage;
LLVMValueRef frag_pos[4];
LLVMTypeRef i1;
LLVMTypeRef i8;
LLVMTypeRef i16;
LLVMTypeRef i32;
LLVMTypeRef i64;
LLVMTypeRef v2i32;
LLVMTypeRef v3i32;
LLVMTypeRef v4i32;
@@ -823,22 +821,22 @@ static void create_function(struct nir_to_llvm_context
*ctx)
add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model
*/
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /*
linear sample */
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /*
linear center */
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /*
linear centroid */
add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex
*/
add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos
x float */
add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos
y float */
add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos
z float */
add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos
w float */
add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /*
front face */
- add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /*
ancillary */
- add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /*
sample coverage */
+ add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /*
ancillary */
+ add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage);
/* sample coverage */
add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
break;
default:
unreachable("Shader stage not implemented");
}
ctx->main_function = create_llvm_function(
ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
ctx->max_workgroup_size,
ctx->options->unsafe_math);
@@ -3970,27 +3968,27 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
} else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
ctx->nctx->shader_info->tcs.uses_prim_id = true;
result = ctx->nctx->tcs_patch_id;
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
ctx->nctx->shader_info->tcs.uses_prim_id = true;
result = ctx->nctx->tes_patch_id;
} else
fprintf(stderr, "Unknown primitive id intrinsic: %d",
ctx->stage);
break;
case nir_intrinsic_load_sample_id:
- result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
+ result = unpack_param(ctx->nctx, ctx->abi->ancillary, 8, 4);
break;
case nir_intrinsic_load_sample_pos:
result = load_sample_pos(ctx->nctx);
break;
case nir_intrinsic_load_sample_mask_in:
- result = ctx->nctx->sample_coverage;
+ result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_front_face:
result = ctx->abi->front_face;
break;
case nir_intrinsic_load_instance_id:
result = ctx->abi->instance_id;
break;
case nir_intrinsic_load_num_work_groups:
result = ctx->nctx->num_work_groups;
break;
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 1c8d0e8..fd62f22 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -38,20 +38,22 @@ enum ac_descriptor_type {
*/
struct ac_shader_abi {
enum chip_class chip_class;
LLVMValueRef base_vertex;
LLVMValueRef start_instance;
LLVMValueRef draw_id;
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
LLVMValueRef front_face;
+ LLVMValueRef ancillary;
+ LLVMValueRef sample_coverage;
/* For VS and PS: pre-loaded shader inputs.
*
* Currently only used for NIR shaders; indexed by variables'
* driver_location.
*/
LLVMValueRef *inputs;
void (*emit_outputs)(struct ac_shader_abi *abi,
unsigned max_outputs,
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 71e559f..7eba137 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4512,22 +4512,24 @@ static void create_function(struct si_shader_context
*ctx)
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTER);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTROID);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_LINE_STIPPLE_TEX);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_X_FLOAT);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_Y_FLOAT);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_Z_FLOAT);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_W_FLOAT);
add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.front_face,
SI_PARAM_FRONT_FACE);
shader->info.face_vgpr_index = 20;
- add_arg_checked(&fninfo, ARG_VGPR, ctx->i32,
SI_PARAM_ANCILLARY);
- add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_SAMPLE_COVERAGE);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
+ &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
+ &ctx->abi.sample_coverage,
SI_PARAM_SAMPLE_COVERAGE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->i32,
SI_PARAM_POS_FIXED_PT);
/* Color inputs from the prolog. */
if (shader->selector->info.colors_read) {
unsigned num_color_elements =
util_bitcount(shader->selector->info.colors_read);
assert(fninfo.num_params + num_color_elements <=
ARRAY_SIZE(fninfo.types));
for (i = 0; i < num_color_elements; i++)
add_arg(&fninfo, ARG_VGPR, ctx->f32);
--
2.9.3
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