From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 10b3630..7de8b10 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -25,20 +25,26 @@
#include "si_shader_internal.h"
#include "ac_nir_to_llvm.h"
#include "tgsi/tgsi_from_mesa.h"
#include "compiler/nir/nir.h"
#include "compiler/nir_types.h"
+static int
+type_size(const struct glsl_type *type)
+{
+ return glsl_count_attribute_slots(type, false);
+}
+
static void scan_instruction(struct tgsi_shader_info *info,
nir_instr *instr)
{
if (instr->type == nir_instr_type_alu) {
nir_alu_instr *alu = nir_instr_as_alu(instr);
switch (alu->op) {
case nir_op_fddx:
case nir_op_fddy:
case nir_op_fddx_fine:
@@ -338,20 +344,24 @@ si_lower_nir(struct si_shader_selector* sel)
}
}
/* Perform lowerings (and optimizations) of code.
*
* Performance considerations aside, we must:
* - lower certain ALU operations
* - ensure constant offsets for texture instructions are folded
* and copy-propagated
*/
+ NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
+ (nir_lower_io_options)0);
+ NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
+
NIR_PASS_V(sel->nir, nir_lower_returns);
NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
static const struct nir_lower_tex_options lower_tex_options = {
.lower_txp = ~0u,
};
NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
--
2.9.3
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