[Mesa-dev] [PATCH 10/22] i965/gen6: Use helper variables for texture surface parameters

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 33 ++++++++++++++++--------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f3efdbc..5f40301 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -324,6 +324,13 @@ brw_update_texture_surface(struct gl_context *ctx,
       return;
    }
 
+   unsigned width = mt->logical_width0;
+   unsigned height = mt->logical_height0;
+   unsigned pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
+   unsigned min_lod = tObj->BaseLevel - mt->first_level;
+   unsigned mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
+
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
                          6 * 4, 32, surf_offset);
 
@@ -366,16 +373,16 @@ brw_update_texture_surface(struct gl_context *ctx,
 
    surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 
-   surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT 
|
-             (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
-             (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+   surf[2] = SET_FIELD(mip_count, BRW_SURFACE_LOD) |
+             SET_FIELD(width - 1, BRW_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, BRW_SURFACE_HEIGHT);
 
-   surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
-             (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
-             (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+   surf[3] = brw_get_surface_tiling_bits(tiling) |
+             SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+             SET_FIELD(pitch - 1, BRW_SURFACE_PITCH);
 
    surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
-              SET_FIELD(tObj->BaseLevel - mt->first_level, 
BRW_SURFACE_MIN_LOD));
+              SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD));
 
    surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 
@@ -657,6 +664,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
+   unsigned width = rb->Width;
+   unsigned height = rb->Height;
+   unsigned pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
    uint32_t *surf;
    uint32_t tile_x, tile_y;
    uint32_t format = 0;
@@ -700,11 +711,11 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
              mt->bo->offset64);
 
-   surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
-             (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+   surf[2] = SET_FIELD(width - 1, BRW_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, BRW_SURFACE_HEIGHT);
 
-   surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
-             (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+   surf[3] = brw_get_surface_tiling_bits(tiling) |
+             SET_FIELD(pitch - 1, BRW_SURFACE_PITCH);
 
    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
 
-- 
1.8.3.1

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