Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 28 ++++++++++++++++-------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index f12f215..759fef5 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -333,11 +333,17 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
- SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
+ surf[4] = SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD((effective_depth - 1),
GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
+ /* As sampling engine does not support the native W-tiling of stencil,
+ * one cannot configure the MSAA support either. Both tiling and sample
+ * indexing are handled by the program.
+ */
+ if (!is_stencil(mt))
+ surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
SET_FIELD(min_lod, GEN7_SURFACE_MIN_LOD) |
mip_count);
@@ -465,8 +471,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
bool is_array = false;
int depth = MAX2(irb->layer_count, 1);
const uint8_t mocs = GEN7_MOCS_L3;
-
- int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
+ const int min_array_element = is_stencil(irb->mt) ?
+ irb->mt_layer : irb->mt_layer / MAX2(mt->num_samples, 1);
GLenum gl_target = rb->TexImage ?
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
@@ -480,8 +486,11 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
intel_miptree_used_for_rendering(irb->mt);
- /* Render targets can't use IMS layout */
- assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+ /* Render targets can't use IMS layout. Stencil in turn gets configured as
+ * single sampled and indexed manually by the program.
+ */
+ if (!is_stencil(irb->mt))
+ assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
assert(brw_render_target_supported(brw, rb));
format = brw->render_target_format[rb_format];
@@ -533,10 +542,13 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) | (pitch - 1);
- surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples,
irb->mt->msaa_layout) |
- min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
+ surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
(depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
+ if (!is_stencil(irb->mt))
+ surf[4] |= gen7_surface_msaa_bits(irb->mt->num_samples,
+ irb->mt->msaa_layout);
+
if (irb->mt->mcs_mt) {
gen7_set_surface_mcs_info(brw, surf,
brw->wm.base.surf_offset[surf_index],
irb->mt->mcs_mt, true /* is RT */);
--
1.8.3.1
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