Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 5f40301..d00a65d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -381,8 +381,14 @@ brw_update_texture_surface(struct gl_context *ctx,
SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
SET_FIELD(pitch - 1, BRW_SURFACE_PITCH);
- surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD));
+ surf[4] = SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD);
+
+ /* As sampling engine does not support the native W-tiling of stencil,
+ * do not configure the MSAA support either. Both tiling and sample
+ * indexing are handled by the program.
+ */
+ if (!is_stencil(mt))
+ surf[4] |= brw_get_surface_num_multisamples(mt->num_samples);
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
@@ -717,7 +723,11 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
surf[3] = brw_get_surface_tiling_bits(tiling) |
SET_FIELD(pitch - 1, BRW_SURFACE_PITCH);
- surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
+ /* Render targets can't use IMS layout. Stencil in turn gets configured as
+ * single sampled and indexed manually by the program.
+ */
+ if (!is_stencil(mt))
+ surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
/* Note that the low bits of these fields are missing, so
--
1.8.3.1
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