Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c9d9614..f3efdbc 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -122,6 +122,27 @@ brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
if (is_render_target) {
*format = BRW_SURFACEFORMAT_R8_UINT;
+ } else {
+ /* Manual sampling of W-tiled surfaces reads one 2x2 pixel block at a
+ * time and the program extracts individual pixels/samples from the
+ * 32-bit integer "behind the scene". In case of msaa 2x2 blocks
+ * represent sample values for particular index - eight samples per
+ * pixel has two 2x2 blocks side-by-side and hence the surface is
+ * configured for 64-bit elements.
+ * This organization prevents the pixel dimensions given to the sampling
+ * engine from exceeding the maximum allowed.
+ */
+ switch (mt->num_samples) {
+ case 0:
+ case 4:
+ *width /= 4;
+ *format = BRW_SURFACEFORMAT_R32_UINT;
+ break;
+ case 8:
+ *width /= 8;
+ *format = BRW_SURFACEFORMAT_R32G32_UINT;
+ break;
+ }
}
}
--
1.8.3.1
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