The IEEE-696 definition of the Phantom line states:- "The Phantom* line is provided for overlaying bus slaves at a common address location. When this line is activated, phantom bus slaves are enabled and normal slaves are disabled."
I read this as, yes, both RAM and port addresses. Normally a total card disappears from the bus if it is monitoring the phantom line, via its board select (BS) line. Do not confuse a master/slave switchover and a phantom line call. The latter is always done by the current master (can be any one of 16 total) . It's up to you how you want your RAM to behave on your CPU board. It can be local to the board -- as for example is the ROM on our Z80 board, or shared with other CPU's. The former has the advantage that it does not get in the way where that CPU is no longer the bus master. If it is visible when the CPU is no longer the bus master, you can still use that RAM. However you will have to phantom out any overlap with other RAM board if present when that slave is the current bus master. Nothing special about access. As I said phantom normally just inactivates a board select line. Unless you are using DRAM's (a whole other situation), memory RD/WR signals should be fine. Take a look at the phantom line on our old 4MB Static RAM board http://s100computers.com/My%20System%20Pages/RAM%20Board/4MG%20RAM%20Board.h tm Hope this helps John From: [email protected] [mailto:[email protected]] On Behalf Of Crusty OMO Sent: Monday, May 5, 2014 6:17 PM To: [email protected] Subject: RE: [N8VEM-S100:3500] Phantom of the S-100 Ok, I have the CPU board and Memory working with the FP. Had trouble with the FP driving all these chips on a single board, so I put in another buffer chip between the FP and the local bus. Fixed a few other timing issues/errors along the way. Now, I have some questions about the Phantom line. When another board asserts the Phantom line, boards that respond to this line will prevent their output to the bus. This output is understood to be from the memory map, but is the Phantom LIne suppose to also nuke access to I/O? Next, if the CPU board has Memory on board and an external board asserts the Phantom line, then should the CPU switch it's input from the local memory to the Data In bus? That would make sense to me. Boards that do assert the Phantom line, do they synchronize the Phantom line with memory read/write cycles? or, I mean to say the State of the CPU, ie, is Phantom allowed to be active during a pSync state? (which happens at the start of every cycle). On the 8080A, the Data Out should have the Status Byte during pSync, how do boards that generate phantom allow for that? Thanks, Josh Bensadon -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
