David, Yes, I am using all 74LS and the board is only running at 2 Mhz. I am going to set up a simple little delay loop using the 2 unused 74LS02 gates and see if that will delay the clock just enough at pin 3 of the flip flop.
Thomas On Monday, June 9, 2014 2:43:44 PM UTC-4, David Fry wrote: > > Thomas, > > I take it that you are only using 74LS series IC's with no 'F' series in > there anywhere, if not then this would seem to confirm timing issue. > > maybe mixing some 'F' series on the 74F07 and 'L' series 74L02 might buy > you some leaway, if not then a resistor/small capacitor as John suggested > would seem to be the way to go. This would need trimming on the logic > analyser for a minimum but safe working delay. > > regards > > David Fry > > On Monday, June 9, 2014 7:13:55 PM UTC+1, Thomas Owen wrote: > >> UPDATE: >> >> If I manually set pin 2 of the flip flop to either high or Low then the >> Drive Select works. >> >> *pin 2 held high, console out DO34,01 changes to Drive B.* >> >> It appears to me that the FF is always clocking in a 0 due to timing on >> the input. >> >> I have two different CPU's in a IMSAI chassis (with front panel). CPU is >> a Cromemco ZPU and the other is the IMSAI 8080 - both exhibit same behavior. >> >> DO0 definitely changes (see the earlier screen shots) for the different >> commands 'QO34,00' and 'QO34,01'. >> >> Thomas >> >> >> >> >> >> On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote: >>> >>> All, >>> I had posted this to the thread dealing with ordering this card, but >>> decided to post a new topic dealing with the problem I have had with final >>> checkout of the board. >>> >>> During assembly the board passed all the 'in progress' checks. The >>> final steps were to output to different ports: >>> >>> >>> I have output the following and everything passes: >>> >>> QO33,80 ; Configures ports A, B and C as output ports >>> QO32,2B ; Selects right hand pair of digits >>> QO30,01; display 01on right digit pair and work through each bit - all ok >>> >>> QO32,2c; Selects middle pair of digits >>> QO30,01; Should display 01 on middle digit pair, work through each bit - >>> all ok >>> >>> QO32,2d; Selects left hand pair of digits >>> QO31,01; Should display 01 on left digit pair, work through each bit - >>> all ok >>> >>> All displays are correct. >>> >>> Now the final step is the Drive Select and that is where I am having >>> trouble: >>> >>> Board always comes up with 'Drive A' selected >>> >>> Now, QO34,0; no change >>> >>> Reset, start again: >>> >>> QO34,1; no change >>> >>> I can never select drive B. >>> >>> Several generous members (thank you David Fry) have made suggestions, >>> and here is where I now stand: >>> >>> My preliminary check this afternoon shows me that there is a timing >>> issue at U15, the 74ls02. Using my logic analyzer and monitoring the >>> inputs and the output (which clocks the drive select flip flop) I see a big >>> timing difference between SEL_SECOND and WR. >>> >>> What this means is that the output of the gate never goes high allowing >>> the bit change to effect drive change/selection. >>> >>> I am going to get some screen shots from the analyzer tomorrow, and if >>> anyone has any suggestions I would greatly appreciate it. >>> >>> Thanks, >>> Thomas >>> >>> -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
