Hi John,

I plan to tonight - btw still have not gotten IDE board to work yet with 
68K (I think the problem is with writing registers - read seems to be OK so 
the pWR* maybe the issue) - though I did get the disk select to work with 
the mods I have made so far.  Also on you monitor code you will have 
problems in your IDEWr routine as you do an ori with a memory location 
which is a port - the 8255 will not be able to do the read modify write so 
you need to do an ori with register and move the register to the port - I 
fell into same trap - I think a long session with Mr. Logic Analyzer and I 
will figure out what is going on.

Dave

On Thursday, July 17, 2014 12:32:58 PM UTC-5, monahanz wrote:
>
> Hi Dave, just wondering if you had a chance to look into this pWR* signal 
> issue on the 68K board. 
>
> John
>
>  
>
>  
>
> *From:* [email protected] <javascript:> [mailto:
> [email protected] <javascript:>] *On Behalf Of *yoda
> *Sent:* Saturday, June 28, 2014 8:20 PM
> *To:* [email protected] <javascript:>
> *Cc:* [email protected] <javascript:>
> *Subject:* Re: [N8VEM-S100:4411] S100 68K issue
>
>  
>
> z80 has plenty of margin - 250ns data valid after pWR* goes hi.  I am 
> seeing about 10 - 20 ns but not consistent.  Need to figure out how to 
> shorten pWR* or get data to be valid longer.  I guess I will be getting 
> intimate with Wilcox book on his S100 state machine.  I believe Pontius 
> experienced that is was very marginal.  Guess you have been lucky John.
>
>  
>
> Dave
>
> On Saturday, June 28, 2014 9:20:46 PM UTC-5, yoda wrote:
>
> Hi John
>
>  
>
> Yes I think we need to get this resolved quickly before we do another 
> round of boards.  I did find in Wilcox's book on page 331 that the chips 
> should be schottky devices which would be U38 and U42 which I have replaced 
> with 74F series - the prop console works but I would not say reliably yet. 
>  I am putting it back on the logic analyzer now.  I also notice compared to 
> that diagram the pWR* path has an extra inverter in it which would cause 
> and extra 7-10 ns delay which may be stretching pWR* out maybe too far.  I 
> want to compare to Z80 board after I take another snapshot on the analyzer 
> - I think pWR* is getting delayed too long.  The circuit you are thinking 
> of in the next post is the one that generates A0 from LDS and uses an RC 
> circuit on one of the legs - that seems to be working ok as the address 
> lines look solid.  I will continue digging and let you know - think we 
> should delay the 68K board until after you get back.  Have a fun vacation
>
>  
>
> Dave
>
> On Saturday, June 28, 2014 6:06:41 PM UTC-5, monahanz wrote:
>
> Dave I have not had a problem with that board with the Propeller Console 
> IO board at all. Have not run it with the IDE board. That said I could only 
> get about 6MHz out of a 10Hz chip. I know Todd is about to order another 
> batch, we should resolve this ASAP
> I'm MIA for two weeks unfortunately
> John
>
> John Monahan ([email protected])
>
> On Jun 28, 2014 3:32 PM, "yoda" <[email protected]> wrote:
>
> Hi
>
>  
>
> Wondering if people have been using the 68K board.   I think I have timing 
> issue because pWR* is going HI at the same time the data is being released. 
>  You can see this in attached LA capture.  I think that is why I am not 
> getting characters from the prop console and probably explains why I have 
> not gotten reliable data from the IDE card either.  The dual serial card 
> and memory work just fine.  I have tried different clocks as well - this 
> one is at 2MHz so that should not be the issue.  Was wondering if someone 
> had seen this and resolved.  I will dig through the schematics and the 
> Wilcox book as well.  I think once I have this resolved, I can get CP/M 68K 
> going.
>
>  
>
> Thanks in advance
>
>  
>
> Dave
>
>  
>
>  
>
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