Hi Brian I would appreciate a scan of the hand-written errata and notes from Dr. Wilcox in general. I think I have it working reliably - just not yet with the IDE board which is kind of crucial. I will be moving the logic analyzer to the 8255 on the IDE board and do some signal analysis. It is entirely possible that I have a bug in the software but I have been over it a dozen times so I still will not rule it out - the most definitive check is what the code is writing appears on the data ports of the 8255 - if not then start back tracing. I will isolate the problem soon - the solution may be another thing that will take time depending on what it is.
Thanks for your help Dave On Friday, July 18, 2014 6:35:08 AM UTC-5, Brian Marstella wrote: > > Dave, > > I have Dr. Wilcox's hand-written errata and notes for the text as I picked > them up a couple of years ago. If I have time this weekend, I'll try to > review and if I find anything significant to the problem I'll scan and post > for you. I haven't started building my 68k board yet, although I have Dr. > Wilcox's original wire-wrapped board. > > Regards, Brian. > > On Thursday, July 17, 2014 10:23:30 PM UTC-4, yoda wrote: > >> Hi John, >> >> Re-wiring the circuit gives no noticeable difference. I see between 40 >> and 50 ns delay of release of data after pWR* going high. I don't know if >> that is enough or not. I attached a typical trace here. If you look at >> pages 331-337 of Wilcox he discusses the circuit and the issue with write. >> The circuit is not the same as in the schematics on page 494-495 as the >> logic and path lengths have been changed. I am not sure what to do - the >> console I/O and serial I/O are working fine but I am not sure on the IDE >> board yet - I need to but the logic analyzer on the 8255 or IDE port and >> look at what data is being put on the ports and make sure it matches what I >> am sending. I probably have a couple of days of debugging here so if you >> want to wait on pushing the design out until I have the IDE board working >> with it, I would feel more comfortable. >> >> Also in your write up in the end you state that jumpering P2 3-4 makes >> all S100 bus I/O have 2 wait states - the way I read the schematic you are >> adding 2 wait states to M1 pgm fetches. I think you want to jumper 4 to 1 >> or 7,9 for 2 waits on I/O accesses. Look at 479 as it gives several >> examples as how to set the jumpers. >> >> The net of above - no matter what frequency you run at, U37, U38, U42 and >> U40 (if you can find one) need to all be F logic. The state machine is >> independent of processor frequency (I think Pontius found that in his bring >> up and is in his reference notes on the wiki). >> >> Dave >> > -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
