>> Roger are you sure you are sending the right configuration codes to the
>> 8255. I don’t want to have to spend
>> time going back and digging into that to find the bits are wrong.
Not much digging required -- lines 44 and 45 of the MYIDE code. 80h sets all
ports to output, and 92h sets port C to output, and ports A&B to input.
>> How familiar are you with the 8255?
Not very. If I have to do parallel, I prefer the Zilog PIO.
>> Absolutely incorrect! RD* & WR* are the generalized bus signals pulsing all
>> the time.
OK ... I looked at the GAL code, and I can see they are derived directly from
the bus. My mistake!
>> If so send personal e-mail.
Personal e-mail on the way.
Roger
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