Plan on using 2 I/O write-cycles to send a bit. This way you will guarantee setup and hold-time margin at the receiving end assuming the receiver captures on rising-edges of clk. For example:
cycle A: data bit 1, clk=0 cycle B: data bit 1, clk=1 cycle A: data bit 2, clk=0 cycle B: data bit 2, clk=1 I use this sequence in my big clock which has a 96-bit shift register (72 bits for hours and minutes hand info), and it's clocked at 200nsec (5Mhz). Despite having a 3 foot-long clock line (yes, it's properly terminated), there are no observable bit errors. BTW, I use an FPGA programmed in Verilog, not a CPU. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/9feb4e5f-547d-407e-b4a9-2292a43d1bc0%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
