Thank you again. Tomorrow I'll move POL from VSS to VDD on all three chips, from the top of the sockets. No other way. Hopefully that will do, since the display seems to update comfortably at better than 100ms so there is no apparent issue with timing. I don't think it's worth the time to investigate calculating the exact timing, at least not yet. Adding two CMOS, 12v inverters between CLK on the three chips would require another IC. Hopefully that won't be necessary.
I'll post an update shortly. And I really do appreciate the help and advice. I was at a dead end with this issue. On Thursday, June 11, 2015 at 1:04:36 AM UTC-4, gregebert wrote: > > According to my read of the datasheet, POL needs to be high in order for > blanking to extinguish all cathodes. That also would explain why sending a > '0' to the HV5530 will cause a cathode to illuminate. So, if you have POL > low you will be attempting to turn-on all cathodes at the same time. The > power supply is probably current-limited so it would prevent all cathodes > from actually glowing. > > Regarding the CLK, the inversion of every-other clk-input is way to > guarantee hold-time is satisfied when shift registers are cascaded, at the > expense of setup time. Basically, the sending device transmits on the > falling-edge of clk, and the receiving device samples on the rising-edge > (because of the added inverter). You have a guaranteed hold-margin of 1/2 > clk cycle. > > > -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/9ffa142c-b692-42fe-b0df-54d2f327da72%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
