Thanks for your comments.

POL is grounded, and serial bits are sent low to light a segment. Using 
analogWrite(blankPin, 200); to enable PWM, most or all segments of all 
Nixies will light. I think sending alternate serial packets will suck too 
much CPU.

I grounded POL following the Nixiechron schematic. Somehow dimming works 
well with that clock. Hopefully the answer is not to connect POL to VCC. 
Traces are under the PLCC socket. 

I don't understand the part about inverting CLK. All of this came from a 
pile of Nixie clock schematics. That is beyond the limit of my knowledge.



On Wednesday, June 10, 2015 at 7:33:07 PM UTC-4, gregebert wrote:
>
> Nice board.
>
> I'm curious why the blanking pin on the HV5530 isn't working. Is it that 
> you dont see any dimming, or is it something else ? Be careful about the 
> setting of the POL pin; if it's at the wrong level you will turn on all 
> cathodes when you attempt to blank the displays.
>
> I'm working on a 14-tube IN-18 clock that uses the HV5530, and I plan to 
> use the blanking pin for dimming. My control logic is entirely FPGA, so I 
> have no issues about software timing, etc.
>
> Although it's inefficient, you could implement a lower-speed PWM by 
> sending alternate serial packets with all cathodes off, then the desired 
> cathodes on, etc. I dont know if your CPU can handle that workload under 
> software control, though.
>
> The datasheet parameters dont specify a *minimum* propagation delay on 
> the DataOut pin (tDLH), and there is a minimum hold-time requirement on the 
> DataIn pin, so it's theoretically not possible to cascade these devices 
> unless you  alternately invert the CLK signal or add delay on the DataIn 
> pin. This wont cause a problem with blanking, but it could cause marginal 
> operation. I chose to alternately invert the CLK signal.
>

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