Alison Schofield wrote: > On Thu, Nov 24, 2022 at 10:35:38AM -0800, Dan Williams wrote: > > In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint > > the represents the memory expander. Unlike a VH topology there is no > > CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this > > as the CXL root object (ACPI0017 on ACPI based systems) targeting the > > host-bridge as a dport, per usual, but then that dport directly hosts > > the endpoint port. > > > > Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd' > > device instance as its immediate child. > > > > Reviewed-by: Alison Schofield <alison.schofi...@intel.com> > > How can this host bridge and device be used? Should I be looking in > the spec to see the limitations on a 1.1 usage?
Yes, CXL 3.0 9.11.8 "CXL Devices Attached to an RCH" is the best starting point. > Expect it to behave like VH topo? Expect graceful failure where it > doesn't? I'm just after a starting point for understanding how the > 1.1 world fits in. The expectation is that an RCH topology is a strict subset of a VH topology. I think of it as VH minus device-interleaving and hotplug. Once you have found the CXL component register block the enabling can be shared between 1.1 and 2.0. So, for example see all the different component registers listed in CXL 3.0 Table 8-22. Where that block is available to "D1" and "D2" the driver enabling can be shared. The only difference is how to find those component registers.
