Alison Schofield wrote: > On Thu, Nov 24, 2022 at 10:35:38AM -0800, Dan Williams wrote: > > In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint > > the represents the memory expander. Unlike a VH topology there is no > > CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this > > as the CXL root object (ACPI0017 on ACPI based systems) targeting the > > host-bridge as a dport, per usual, but then that dport directly hosts > > the endpoint port. > > > > Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd' > > device instance as its immediate child. > > > > Reviewed-by: Alison Schofield <alison.schofi...@intel.com> > > How can this host bridge and device be used?
Answering the direct question... it's not good for much more than testing enumeration. The expectation is that RCH hosts will be configured by BIOS and most likely Linux driver only ever needs to read the configuration, not change it. So most of the excitement from a cxl_test perspective is in the enumeration. The rest of the RCH enabling will be for error handling for errors that impact regions set up by BIOS. That testing will need hardware, or QEMU, but I do not expect RCH topologies to show up in QEMU any time soon, if ever.
