On Monday 21 February 2005 22:20, Timothy Miller wrote:
> I had mentioned earlier that I've been tied up with the business
> aspects of the OGP, and I thought some of you might be interested in
> hearing about what's going on and have some discussion on it.

Definitely, please keep us posted. I've no doubt the hardware and software 
side of it can get done. Without a viable business plan we're nowhere though.

> The retail graphics board will be affected such that the board will
> now sell with a much lower retail price.  Furthermore, we're looking
> into the idea of selling the retail board through partners who
> specialize in that so as to further reduce the price.  The result will
> be a MUCH less expensive retail product.  There is also a likelihood
> that we'll have greater freedom in terms of power consumption versus
> speed.

Excellent! I'm not that interested in the FPGA board, because I know I won't 
have time to get into it, and it will probably require using proprietary 
tools for programming it anyway.

> At the same time, we don't want to leave behind those who would like
> to tinker.  In any case, we will have to design a prototype board, and
> so our plan is to sell that as a product in its own right.  Some
> changes to it include possibly separating the host controller out into
> a separate chip so that you can reprogram the main FPGA as you like
> without affecting your ability to reprogram it again.  Putting it
> another way, the prototype will be designed with features that lend
> themselves more effectively towards experimentation.  The lower sales
> volumes of this product will increase its cost relative to the
> original plan.  If, however, we get higher volume than expected, the
> price will go down, especially for bulk orders.

There's nothing to compete with anyway, so it's okay if it got more expensive. 
If it's a toy for the interested geek then price is probably not going to be 
that much of a problem :-).

How does an ASIC compare to an FPGA? I guess it doesn't have any constraints 
in terms of "amount of subcomponent X" so we'll need to optimise for chip 
surface size rather than number of multipliers and/or LUTs?

Lourens
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