> On Monday 21 February 2005 22:20, Timothy Miller wrote: > How does an ASIC compare to an FPGA? I guess it doesn't have any > constraints > in terms of "amount of subcomponent X" so we'll need to optimise for chip > surface size rather than number of multipliers and/or LUTs? >
Usually you have a "budget" and performance goal. Instead of being enclosed by the number of cells, you know that fewer is cheaper. So if you reach the performance with less gate you earn more money. The buget could be gate count (==area) and power (~10W to be fan-less) for a choosed technology with a target of xxx Mhz and the specification of the software model. With 0.18�, you could target 300Mhz with the problem of power consumption. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
