Just wondering, will it be possible to use only one of the memory
controller in the chip for all memory access? Because if you make the
chip into an asic and people integrated them in some system, they will
not always want to use 4 memory chip, only one. Like in a server(on the
mobo) or a portable device.
Timothy Miller wrote:
The memory controller will be designed with a set of "ports" which are
connections to agents that need access to memory. I then prioritizes
requests and accesses memory as necessary. In fact, there'll be four
memory controllers working somewhat independently.
Anyhow, each port will have its own very small cache. This way,
accessing the same pixel twice does not require a re-read of memory.
(Although the two texture units will share a port, I think I want to
give each one its own cache.)
Caching with low overhead can result in non-coherency. Therefore,
certain things like bitblts will need to be able to specify that the
read caches are to be flushed before reading starts (and other similar
things).
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