On Thu, 17 Mar 2005 23:31:45 -0500
Timothy Miller <[EMAIL PROTECTED]> wrote:
> I wasn't clear. When I say that the GPU "polls the write pointer", I
> mean, "the GPU does a DMA read of a word in host memory that contains
> the write pointer".
The pointer here is a 64 bit value, right ?
How do you garantee atomicity of the read ?
Ie i see here a race condition on 32 bit systems,
when the host updates the pointer.
And how does it work with cache ? Ie, is the cache
flushed if the pci buss accesses a region of the
host memory which contents were modified in the cache ?
Attila Kinali
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