On Thursday 05 May 2005 18:45, Eric Smith wrote: > Daniel wrote: > > As I understand it, only the "net list loader" (is that what they > > call it?) that loads the synthesized logic into the FPGA is not > > available as a free tool. > > No. The free tools include an unrestricted "Impact", which is the > FPGA loader. It can load the 3S4000 without any difficulty. > However, I suspect that end users of the card would never use Impact.
Why? Because we will provide our own logic-loading path, e.g., over PCI? > And in any case, there already exist free alternatives to Impact for > the XC3S series parts. OK, so that answers that. > What Webpack 7.1i cannot do is synthesize, place, and route a design > for a 3S4000. So anyone doing RTL development would either need to > buy the full ISE package, or use Webpack 6.3i with the service pack, > since that has full 3S4000 support. Right, so our job should be to convince Xilinx to let the webpack handle the 3S4000. > Since the RTL is not initially going to be publicly available, it > sounds like only a few people would need to do that. When the RTL is > GPL'd or LGPL'd at a later date, then a lot more people will want to > have no-charge tools for development. We need a commitment from Xilinx _before_ we go ahead. Regards, Daniel _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
