On 5/25/05, Viktor Pracht <[EMAIL PROTECTED]> wrote: > Hi > > We were discussing the VGA nanocontroller on IRC, and figured out its > usefulness depends on the available RAM bandwidth. Extreme examples: > * An 8 bit path shared for instructions and code results in about 2 FPS. > * Independent 32 bit paths for instructions and data result in 32 FPS. > > So, the question is (mainly to Timothy): how could the raw VRAM > interface look like, how could the cached RAM interface look like, and > what bandwidths can we expect from them? > > And, considering that the 4 RAM chips prefer long data streams, which is > the exact opposite of heavily self-modifying nanocontroller code, what > are the latencies for random access?
I've been thinking about it, and while I really like the idea of instructions being lookup tables in RAM, it may not give us the performance we need. Things will already be slow. SO, I suggest we develop a simple processor and use an FPGA RAM block to store both nearly 500 instructions and the register file. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
