I found one typo in my first pass through. Mind you, I don't know
Verilog or VHDL so if there is an error in something specific to the
description language, I may not catch it.
I must say, it is pretty interesting to see the diagram I drew up
reduced to something I can look at and say "Well, yeah. That is all it
does."
Patrick M
<snip>
// Stage 1
// Peform right shift
wire [15:0] shift0 = {source_byte, 8'b0} >> rotate;
wire [7:0] shift1 = shift0[15:8] | shift[7:0];
Shouldn't this be: wire [7:0] shift1 = shift0[15:8] | shift0[7:0];
reg [7:0] source_plane0a;
always @(posedge clock) begin
plane0a <= shift1;
end
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