Am Sonntag, den 12.06.2005, 21:53 -0400 schrieb Timothy Miller:
> And I wonder if there isn't a better way to do a rotate in verilog
> that the synthesizer will make sense of. You know, every time I try
> to so something clever with shifters, like manually code a barrel
> shifter, I always get a much worse result than if I just use the >> or
> << operator in verilog.
The following is the smallest "barrel rotater" I can think about:
wire [7:0] o0 = rotate[0] ? {in[6:0], in[ 7 ]} : in;
wire [7:0] o1 = rotate[1] ? {o0[5:0], o0[7:6]} : o0;
wire [7:0] o2 = rotate[2] ? {o1[3:0], o1[7:4]} : o1;
always @(posedge clock) out <= o2;
It produces 24 2-to-1 MUXes for the wires and an 8 bit register for the
output. Since your code with the >> operator produces exactly the same
result, I wonder what you mean with "a better way".
> Something in the back of my mind is telling me that there are <<< and
> >>> operators in either VHDL or Verilog, but I cannot remember what
> they do... and google chokes on that.
There isn't: http://www.verilog.com/VerilogBNF.html#REF149
But VHDL has rol and ror:
http://opensource.ethz.ch/emacs/vhdl93_syntax.html#pred204
- Viktor Pracht
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