On 11/29/05, Peter TB Brett <[EMAIL PROTECTED]> wrote: > > I'm afraid I'm not well-versed enough in Verilog or high-speed design to > help you out, I'm afraid. Ideally you should keep the probability of > timing violations low enough that you never need double-registering within > your synchronous logic, but at the clock speeds you're designing for that > may not be practical or even realistic. >
This sync fifo is intended to handle cases where there is no fixed relationship between the two clock domains. For instance, PCI might be at 33.333MHz and the other end of the FIFO might be going at 200MHz, but those are just approximate, and the clock generators are completely unrelated. That means there will be drift and jitter between them that will make the clock edges occur too close on a regular enough basis. I'm also being conservative because although I have some sense of what'll happen if the signals are register-to-register, I have no idea what will happen if you put combinatorial logic in between them. I think I'll just not take the risk. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
