Timothy Miller wrote: > This sync fifo is intended to handle cases where there is no fixed > relationship between the two clock domains. For instance, PCI might > be at 33.333MHz and the other end of the FIFO might be going at > 200MHz, but those are just approximate, and the clock generators are > completely unrelated. That means there will be drift and jitter > between them that will make the clock edges occur too close on a > regular enough basis.
Oops, sorry, on the projects I've worked on a 'sync FIFO' has been synchronous in that both ends are clocked from the same clock -- so I had the wrong end of the stick. > I'm also being conservative because although I have some sense of > what'll happen if the signals are register-to-register, I have no idea > what will happen if you put combinatorial logic in between them. I > think I'll just not take the risk. Yes, in this case I most certainly _would_ add an extra register in for safety's sake, and suffer the small latency penalty. Peter -- Quake II build tools: http://peter-b.co.uk/ Latest QuArK: http://quark.sourceforge.net/LatestVersion v2sw6YShw7ln5pr6ck3ma8u7Lw3+2m0l7CFi6e4+8t4Eb8Aen4g6Pa2Xs5MSr5p4 hackerkey.com _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
