On 11/30/05, Peter TB Brett <[EMAIL PROTECTED]> wrote:
>
> Timothy Miller wrote:
>
> > This sync fifo is intended to handle cases where there is no fixed
> > relationship between the two clock domains.  For instance, PCI might
> > be at 33.333MHz and the other end of the FIFO might be going at
> > 200MHz, but those are just approximate, and the clock generators are
> > completely unrelated.  That means there will be drift and jitter
> > between them that will make the clock edges occur too close on a
> > regular enough basis.
>
> Oops, sorry, on the projects I've worked on a 'sync FIFO' has been
> synchronous in that both ends are clocked from the same clock -- so I had
> the wrong end of the stick.

That's okay.  I made up the name and didn't give it much thought.  I
called it that because in TROZ, we developed a 'synchronizer' that was
able to move a piece of data safely between any two clock domains, and
a fifo that had synchronizers in it to pass fifo head/tail back and
forth were then called 'sync fifos'.

Perhaps someone can suggest a better name?  :)

>
> > I'm also being conservative because although I have some sense of
> > what'll happen if the signals are register-to-register, I have no idea
> > what will happen if you put combinatorial logic in between them.  I
> > think I'll just not take the risk.
>
> Yes, in this case I most certainly _would_ add an extra register in for
> safety's sake, and suffer the small latency penalty.

The latency penalty for this FAR less than what we did in TROZ.  When
going from 33MHz to 100MHz, the synchronizer would have a latency of 9
cycles.  Part of that was because the synchronizer was TOO generic. 
Part of it was because I was transporting _binary_ head/tail, so we
had to be more careful with it.  Having only one bit change at a time
with the gray codes helps massively.

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