Timothy Miller wrote:
On 3/17/06, Dieter <[EMAIL PROTECTED]> wrote:
Perhaps we'll have to wait for the next generation product before we
can do these things. Only then will we be trying to get good game
performance anyhow, where things like gamma 1 matter, requiring more
bits per channel.
Games? Graphic artists seem to be the main users demanding color depth
and calibration.
Good point. We would like to support those people. I'm convinced.
So now, how do we do it? :)
As I said before, you need all of the data inputs of the DACs connected
to the FPGA. IIUC, we are short on pins. The problem here seems to be
the LVDS signals that take 2 pins each. I don't see 0.5 GHz signals
driving long traces as a good idea. They would have to be strip lines
terminated at both ends. LVDS drivers would work and we would probably
gain some advantages compared with using the FPGA to drive the LVDS
lines, but that is going to be another $30 or so to populate the HiRes
output for 12 bits.
Now that we have opened the box, I notice that Maxim also makes 14 and
16 bit versions of the DAC, so should the Board be able to accept these
since they are pin compatible?
You need 3x256x16 bits of memory for the palate which can be bypassed.
Either the data in video memory is used as the addresses to the three
blocks of memory and the data in the palate memory drives the DACs or
the memory is bypassed and the date in video memory drives the high 8
bits of the DACS and the low bits are driven with ones. The board
should boot up in the bypass mode. Then you need to be able to write to
the palate memory either as 8 bits per color (the high 8 bits) (and fill
the low bits with 1s for backward compatibility) or as 16 bits per
color. I think that the rest is software.
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