Thanks for all the suggestions in this post. As Tim mentioned, we are severely pin constrained on the FPGA which prevented me hooking all the DAC bits to the FPGA.
I thought about the single ended to LVDS buffer solution mentioned by Jack. TI do some buffers that can handle the single ended speed and are fairly cheap. At the time, I did not think 10 bits was such a big issue, it added $10 to the price of the card and I had (and still have) concerns as to whether we can fit all the buffers in the space. But it may be possible if everybody thought it was really necessary. An alternative to the LVDS buffer idea would be to reduce the number of pins we have set aside for the local PCI interface. The present schematic has 12 uncommited control pins connecting the PCI bridge in the small FPGA to the big FPGA (in addition to data, enables and clock). The pins are uncommitted because we are not sure exactly what control interface we want here. If we could free up some of the 12 pins, I could redo the pinout to provide more data pins to the DAC. Any thoughts Tim ? Howard _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
