On Wed, Mar 22, 2006 at 01:17:57PM +0100, Hans Kristian Rosbach wrote:
>
> Also, would not these pins be less vulnerable to noise than the
> ones at the other far end, thus maybe routing would not need to be
> so strict? After all, the more bits you get, each one will have less
> and less actual impact on the image. So my logic is that the first
> bit toggles a color value of 0/128, so it is absolutely critical to
> get this one right. But the 9'th bit toggles 0/0.5 so some deviance
> probably would not be noticed unless it's more wrong than right.
In an analog situation, that would often be true. For instance, in
the design of a simple DAC ladder network, more tolerance error and ringing
is acceptable on the lower bits than on the higher ones.
This is a digital situation, though. When the clock edge strobes
the data word into the DAC registers, each bit has either settled at the
register input or it hasn't, so after the clock the bit will be either
completely correct in the register or completely wrong. So every bit's
track on the board must meet the appropriate design rules for impedance,
length, and stray reactive loading. Also, the very high clock rate makes
the transmission line delay through the data and clock tracks a significant
item in the total timing budget. It's necessary to account for the skew
between the clock edge and each bit, when calculating timing margins. It
would almost certainly be necessary to make every bit line the same length,
or close to it, then adjust the delay in the clock line to fit. The signals
coming the shortest distances would require some extra bends so that the
transmission line delay is the same as the signals coming from more distant
pins.
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